Intel® FPGA SDK for OpenCL™: Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

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ID 683435
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide x
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform 1.2. Porting the Reference Platform to Your SoC FPGA Board 1.3. Software Support for Shared Memory 1.4. FPGA Reconfiguration 1.5. Building an SD Flash Card Image 1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA 1.7. Known Issues 1.8. Document Revision History
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform x
1.1.1. Cyclone V SoC Development Kit Reference Platform Board Variants 1.1.2. Content of the Cyclone V SoC Development Kit Reference Platform 1.1.3. Relevant Features of the Cyclone V SoC Development Kit
1.1.3. Relevant Features of the Cyclone V SoC Development Kit x
1.1.3.1. Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions
1.2. Porting the Reference Platform to Your SoC FPGA Board x
1.2.1. Updating a Ported Reference Platform
1.4. FPGA Reconfiguration x
1.4.1. FPGA System Architecture Details
1.5. Building an SD Flash Card Image x
1.5.1. Modifying an Existing SD Flash Card Image 1.5.2. Creating an SD Flash Card Image
1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA x
1.6.1. Recompiling the Linux Kernel 1.6.2. Compiling and Installing the OpenCL Linux Kernel Driver
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

1.1.3. Relevant Features of the Cyclone V SoC Development Kit

The following list highlights the Cyclone® V SoC Development Kit components and features that are relevant to the Intel® FPGA SDK for OpenCL™ :

  • Dual-core ARM® Cortex®-A9 CPU running 32-bit Linux.
  • Advanced eXtensible Interface (AXI) bus between the HPS and the FPGA core fabric.
  • Two hardened DDR memory controllers, each connecting to a 1 gigabyte (GB) DDR3 SDRAM.
    • One DDR controller is accessible to the FPGA core only (that is, FPGA DDR).
    • The other DDR controller is accessible to both the HPS and the FPGA (that is, HPS DDR). This shared controller allows free memory sharing between the CPU and the FPGA core.
  • The CPU can reconfigure the FPGA core fabric.

Section Content
Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions

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