AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683428
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Static Update Partial Reconfiguration Tutorial Revision History
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Add the Partial Reconfiguration Controller IP 1.5.5. Step 5: Define Personas 1.5.6. Step 6: Create Revisions 1.5.7. Step 7: Compile the Base Revision 1.5.8. Step 8: Set Up PR Implementation Revisions 1.5.9. Step 9: Change the SUPR Logic 1.5.10. Step 10: Program the Board 1.5.11. Modifying the SUPR Partition
1.5.4. Step 4: Add the Partial Reconfiguration Controller IP x
1.5.4.1. Update the Top-Level Design
1.5.6. Step 6: Create Revisions x
1.5.6.1. Setting the Base Revision 1.5.6.2. Creating Implementation Revisions
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board

1.5.4.1. Update the Top-Level Design

Update the top.sv file with the PR_IP instance:
  1. To add the pr_ip instance to the top-level design, uncomment the following code block in the top.sv file: 
    pr_ip u_pr_ip
    (
        .clk           (clock),
        .nreset        (1'b1),
        .freeze        (freeze),
        .pr_start      (1'b0),            // ignored for JTAG
        .status        (pr_ip_status),
        .data          (16'b0),
        .data_valid    (1'b0),
        .data_ready    ()
    );
  2. To force the output ports to logic 1 during reconfiguration, use the freeze control signal output from PR_IP. Uncomment the following lines of code: 
    assign led_two_on_w    = freeze ? 1'b1 : pr_led_two_on;
assign led_three_on_w  = freeze ? 1'b1 : pr_led_three_on;
  3. To assign an instance of the default persona (blinking_led), update the top.sv file with the following block of code: 
    blinking_led u_blinking_led
    (
        .led_two_on    (pr_led_two_on),
        .led_three_on  (pr_led_three_on),
        .clock         (clock)
        .counter       (count_d)
    );
    Figure 7. Partial Reconfiguration IP Core Integration
Level Two Title