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1.5.1. Step 1: Getting Started
1.5.2. Step 2: Create Design Partitions
1.5.3. Step 3: Allocate Placement and Routing Regions
1.5.4. Step 4: Add the Partial Reconfiguration Controller IP
1.5.5. Step 5: Define Personas
1.5.6. Step 6: Create Revisions
1.5.7. Step 7: Compile the Base Revision
1.5.8. Step 8: Set Up PR Implementation Revisions
1.5.9. Step 9: Change the SUPR Logic
1.5.10. Step 10: Program the Board
1.5.11. Modifying the SUPR Partition
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1.1. Tutorial Requirements
This tutorial requires the following:
- Basic familiarity with the Intel® Quartus® Prime Pro Edition FPGA implementation flow and project files.
- Installation of Intel® Quartus® Prime Pro Edition version 19.1, with Intel® Arria® 10 device support.
- For FPGA implementation, a JTAG connection with the Intel® Arria® 10 GX FPGA development board on the bench.
- Download Reference Design Files.