AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683428
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Static Update Partial Reconfiguration Tutorial Revision History
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Add the Partial Reconfiguration Controller IP 1.5.5. Step 5: Define Personas 1.5.6. Step 6: Create Revisions 1.5.7. Step 7: Compile the Base Revision 1.5.8. Step 8: Set Up PR Implementation Revisions 1.5.9. Step 9: Change the SUPR Logic 1.5.10. Step 10: Program the Board 1.5.11. Modifying the SUPR Partition
1.5.4. Step 4: Add the Partial Reconfiguration Controller IP x
1.5.4.1. Update the Top-Level Design
1.5.6. Step 6: Create Revisions x
1.5.6.1. Setting the Base Revision 1.5.6.2. Creating Implementation Revisions
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board

1.6. Static Update Partial Reconfiguration Tutorial Revision History

Document Version Intel® Quartus® Prime Version Changes
2019.07.15 19.1.0
  • Changed default file export location from output_files to project directory.
  • Described new reserved core partition type and related GUI.
  • Updated Design Partition Window descriptions and screenshots for column display button and new partition properties.
2018.10.12 18.1.0
  • Updated Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP name to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  • Added information about automated .qdb partition export to "Compile the Base Revision."
  • Added output_files directory to output paths.
  • Removed note about new simplified flow.
2018.06.18 18.0.0
  • Corrected syntax error in Define Personas topic code example.
  • Corrected syntax error in Change the SUPR Logic code example.
  • Updated screenshot in Change the SUPR Logic.
2018.05.07 18.0.0
  • Removed descriptions of obsolete synthesis-only revisions and corresponding personas. Replaced with latest simplified flow instructions.
  • Renamed PR revision names to match simplified PR flow.
  • Updated official name of Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP.
  • Added .qsf setting to automatically generate PR bitstream files after compilation.
2017.11.06

17.1.0

Initial release of the document.
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