Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 11/17/2023
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Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. LL Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

4.4.7. Unidirectional Feature

The MAC TX implements the unidirectional feature as specified by clause 66 in the IEEE802.3 specification. This is an optional feature supported only in 10G, 1G/10G, and 1G/2.5G/10G core variants. When you enable this feature, two output ports—unidirectional_en, unidirectional_remote_fault_dis— and two register fields—UniDir_En (Bit 0), UniDirRmtFault_Dis (Bit 1)— are accessible to control the TX XGMII interface.

Table 15.  Register Field and Link Status
Bit 0 Register Field Bit 1 Register Field Link Status TX XGMII Interface Behavior
Don't care Don't care No link fault Continue to allow normal packet transmission.
0 Don't care Local fault Immediately override the current content with remote fault sequence.
1 0 Local fault Continue to send packet if there is one. Otherwise, override the IPG/IDLE bytes with remote fault sequence.4
1 1 Local fault Continue to allow normal packet transmission (similar to no link fault).
0 Don't care Remote fault Immediately override the current content with IDLE control characters.
1 Don't care Remote fault Continue to allow normal packet transmission (similar to no link fault).
4 At least a full column of IDLE (four IDLE characters) must precede the remote fault sequence.
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