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1. About this Document
2. Streaming DMA AFU Description
3. Memory Map and Address Spaces
4. Software Programming Model
5. Running the AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. Streaming DMA Accelerator Functional Unit User Guide Archive
9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide
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1.4. Acceleration Glossary
Term | Abbreviation | Description |
---|---|---|
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs | Acceleration Stack | A collection of software, firmware and tools that provides performance-optimized connectivity between an Intel® FPGA and an Intel® Xeon® processor. |
Intel® FPGA Programmable Acceleration Card | Intel FPGA PAC | PCIe* FPGA accelerator card. Contains an FPGA Interface Manager (FIM) that pairs with an Intel® Xeon® processor over the PCIe* bus. |
OPAE_PLATFORM_ROOT | A Linux shell environment variable set up during the process of installing the OPAE SDK delivered with the Acceleration Stack. |