NCO IP Core: User Guide

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ID 683406
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. About the NCO IP Core 2. NCO IP Core Getting Started 3. NCO IP Core Functional Description A. NCO IP Core User Guide Document Archives 4. Document Revision History
1. About the NCO IP Core x
1.1. Intel® DSP IP Core Features 1.2. NCO IP Core Features 1.3. DSP IP Core Device Family Support 1.4. NCO IP Core MegaCore Verification 1.5. NCO IP Core Release Information 1.6. NCO IP Core Performance and Resource Utilization
2. NCO IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. NCO IP Core Functional Description x
3.1. NCO IP Core Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Core Parameters 3.8. NCO IP Core Interfaces and Signals
3.1. NCO IP Core Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Core Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Core Interfaces and Signals x
3.8.1. Avalon-ST Interfaces in DSP IP Cores 3.8.2. NCO IP Core Signals 3.8.3. NCO IP Core Timing Diagrams
1. About the NCO IP Core
2. NCO IP Core Getting Started
3. NCO IP Core Functional Description
A. NCO IP Core User Guide Document Archives
4. Document Revision History

3.8.2. NCO IP Core Signals

Table 11.  NCO IP Core Signals
Signal Direction Description
address[2:0] Input Address of the 16 phase increment registers when frequency hopping is enabled.
clk Input Clock.
clken Input Active-high clock enable.
freq_mod_i [F-1:0] Input Optional frequency modulation input. You can specify the modulator resolution F in IP Toolbench.
freq_sel[log 2N-1:0] input Use to select one of the phase increment registers (that is to select the hopping frequencies), when frequency hopping is enabled. N is the depth.
phase_mod_i [P-1:0] Input Optional phase modulation input. You can specify the modulator precision P in Ithe wizard.
phi_inc_i [A-1:0] Input Input phase increment. You can specify the accumulator precision A in the wizard.
reset_n Input Active-low asynchronous reset.
write_sig Input Active-high write signal when frequency hopping is enabled.
in_data Output In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST input data signals.
fcos_o [M-1:0] Output Optional output cosine value (when dual output is selected). You can specify the magnitude precision M in IP Toolbench.
fsin_o [M-1:0] Output Output sine value. You can specify the magnitude precision M in IP Toolbench.
out_valid Output Data valid signal. Asserted by the MegaCore function when there is valid data to output.
out_data Output In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST output data signals.
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