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Ixiasoft
3.8.2. NCO IP Core Signals
Signal | Direction | Description |
---|---|---|
address[2:0] | Input | Address of the 16 phase increment registers when frequency hopping is enabled. |
clk | Input | Clock. |
clken | Input | Active-high clock enable. |
freq_mod_i [F-1:0] | Input | Optional frequency modulation input. You can specify the modulator resolution F in IP Toolbench. |
freq_sel[log 2N-1:0] | input | Use to select one of the phase increment registers (that is to select the hopping frequencies), when frequency hopping is enabled. N is the depth. |
phase_mod_i [P-1:0] | Input | Optional phase modulation input. You can specify the modulator precision P in Ithe wizard. |
phi_inc_i [A-1:0] | Input | Input phase increment. You can specify the accumulator precision A in the wizard. |
reset_n | Input | Active-low asynchronous reset. |
write_sig | Input | Active-high write signal when frequency hopping is enabled. |
in_data | Output | In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST input data signals. |
fcos_o [M-1:0] | Output | Optional output cosine value (when dual output is selected). You can specify the magnitude precision M in IP Toolbench. |
fsin_o [M-1:0] | Output | Output sine value. You can specify the magnitude precision M in IP Toolbench. |
out_valid | Output | Data valid signal. Asserted by the MegaCore function when there is valid data to output. |
out_data | Output | In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST output data signals. |