NCO IP Core: User Guide

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ID 683406
Date 11/06/2017
Public

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Document Table of Contents
Document Table of Contents x
1. About the NCO IP Core 2. NCO IP Core Getting Started 3. NCO IP Core Functional Description A. NCO IP Core User Guide Document Archives 4. Document Revision History
1. About the NCO IP Core x
1.1. Intel® DSP IP Core Features 1.2. NCO IP Core Features 1.3. DSP IP Core Device Family Support 1.4. NCO IP Core MegaCore Verification 1.5. NCO IP Core Release Information 1.6. NCO IP Core Performance and Resource Utilization
2. NCO IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. NCO IP Core Functional Description x
3.1. NCO IP Core Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Core Parameters 3.8. NCO IP Core Interfaces and Signals
3.1. NCO IP Core Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Core Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Core Interfaces and Signals x
3.8.1. Avalon-ST Interfaces in DSP IP Cores 3.8.2. NCO IP Core Signals 3.8.3. NCO IP Core Timing Diagrams
1. About the NCO IP Core
2. NCO IP Core Getting Started
3. NCO IP Core Functional Description
A. NCO IP Core User Guide Document Archives
4. Document Revision History

1.3. DSP IP Core Device Family Support

Intel offers the following device support levels for Intel FPGA IP cores:

  • Advance support—the IP core is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
  • Preliminary support—Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution.
  • Final support—Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. You can use it in production designs.
Table 1.  DSP IP Core Device Family Support
Device Family Support
Arria® II GX Final
Arria II GZ Final
Arria V Final
Intel® Arria® 10 Final
Cyclone® IV Final
Cyclone V Final
Intel® Cyclone® 10 Final
Intel® MAX® 10 FPGA Final
Stratix® IV GT Final
Stratix IV GX/E Final
Stratix V Final
Intel® Stratix® 10 Advance
Other device families No support
Level Two Title