Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 11/25/2022
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Document Table of Contents
Document Table of Contents x
1. About This IP 2. Getting Started with Intel FPGA IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
1. About This IP x
1.1. Release Information 1.2. Device Family Support 1.3. Features 1.4. 10/100/1000 Ethernet MAC Versus Small MAC 1.5. High-Level Block Diagrams 1.6. Example Applications 1.7. IP Verification 1.8. Performance and Resource Utilization
1.7. IP Verification x
1.7.1. Optical Platform 1.7.2. Copper Platform
2. Getting Started with Intel FPGA IPs x
2.1. Design Walkthrough 2.2. Generated Files
2.1. Design Walkthrough x
2.1.1. Creating a New Intel® Quartus® Prime Project 2.1.2. Generating a Design Example or Simulation Model 2.1.3. Simulating the System 2.1.4. Compiling the Triple-Speed Ethernet Intel® FPGA IP Design 2.1.5. Programming an FPGA Device
2.2. Generated Files x
2.2.1. Design Constraint File No Longer Generated
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. Timestamp Options 3.5. PCS/Transceiver Options
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA 4.3. Intel FPGA IEEE 1588v2 4.4. Deterministic Latency
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.12. PHY Management (MDIO) x
4.1.12.1. MDIO Connection 4.1.12.2. MDIO Frame Format
4.1.13. Connecting MAC to External PHYs x
4.1.13.1. Gigabit Ethernet 4.1.13.2. Programmable 10/100 Ethernet 4.1.13.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
4.2.10. PHY Power-Down x
4.2.10.1. Power-Down in PCS Variations with Embedded PMA
4.3. Intel FPGA IEEE 1588v2 x
4.3.1. IEEE 1588v2 Supported Configurations 4.3.2. IEEE 1588v2 Features 4.3.3. IEEE 1588v2 Architecture 4.3.4. IEEE 1588v2 Transmit Datapath 4.3.5. IEEE 1588v2 Receive Datapath 4.3.6. IEEE 1588v2 Frame Format
4.3.6. IEEE 1588v2 Frame Format x
4.3.6.1. PTP Frame in IEEE 802.3 4.3.6.2. PTP Frame over UDP/IPv4 4.3.6.3. PTP Frame over UDP/IPv6
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.8. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals 6.1.1.10. ECC Status Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals 6.1.3.4. ECC Status Signals
6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) x
6.1.4.1. GMII Clock Signals 6.1.4.2. E-Tile Transceiver Native PHY Signals
6.1.5. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) x
6.1.5.1. F-Tile Transceiver Direct PHY Signals
6.1.8. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals x
6.1.8.1. Deterministic Latency Clock Signals 6.1.8.2. Deterministic Latency Datapath Signals 6.1.8.3. Deterministic Latency Control and Status Interface Signals 6.1.8.4. Deterministic Latency Interface Signals 6.1.8.5. IEEE 1588v2 PCS TX PTP Alignment Interface Signals
6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
6.1.10.1. 1.25 Gbps Serial Interface 6.1.10.2. Transceiver Native PHY Signal 6.1.10.3. Intel® Arria® 10 Transceiver Native PHY Signals 6.1.10.4. SERDES Control Signals 6.1.10.5. Intel LVDS Transmitter and Receiver Soft-CDR I/O Signals
6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
6.1.11.1. IEEE 1588v2 RX Timestamp Signals 6.1.11.2. IEEE 1588v2 TX Timestamp Signals 6.1.11.3. IEEE 1588v2 TX Timestamp Request Signals 6.1.11.4. IEEE 1588v2 TX Insert Control Timestamp Signals 6.1.11.5. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 6.1.11.6. IEEE 1588v2 PCS Phase Measurement Clock Signal 6.1.11.7. IEEE 1588v2 PHY Path Delay Interface Signals
6.1.12. 1000BASE-X/SGMII PCS Signals x
6.1.12.1. PCS Control Interface Signals 6.1.12.2. PCS Reset Signals 6.1.12.3. MII/GMII Clocks and Clock Enablers 6.1.12.4. GMII 6.1.12.5. MII 6.1.12.6. SGMII Status Signals
6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.13.1. Clock Enablers 6.1.13.2. PCS Reset Signals 6.1.13.3. TBI Interface Signals
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive 6.2.9. IEEE 1588v2 Timestamp
7. Design Considerations x
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA x
7.1.1. MAC and PCS With GX Transceivers 7.1.2. MAC and PCS With LVDS Soft-CDR I/O
7.5. Migrating From Old to New User Interface For Existing Designs x
7.5.1. Exposed Ports in the New User Interface
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
10. Software Programming Interface x
10.1. Driver Architecture 10.2. Directory Structure 10.3. PHY Definition 10.4. Using Multiple SG-DMA Descriptors 10.5. Using Jumbo Frames 10.6. API Functions 10.7. Constants
10.6. API Functions x
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About This IP
2. Getting Started with Intel FPGA IPs
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Software Programming Interface
11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters

1.8. Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet Intel® FPGA IP are obtained by compiling the Triple-Speed Ethernet Intel® FPGA IP using the Intel® Quartus® Prime software targeting a given device. The fMAX of all configurations is more than 125 MHz.
Table 5.  Resource Utilization for Triple-Speed Ethernet for Intel® Agilex™ DevicesThe following estimates are obtained by targeting the Intel® Agilex™ (AGFB014R24A3E3VR0) device.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

 2048x32 4051 5634 21
2048x8 3865 5442 16
10/100 Mbps Small MAC

MII.

Full- and half-duplex only.

 2048x32 1445 2120 11
1000 Mbps Small MAC

GMII.

Full-duplex only.

 2048x32 1178 1937 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

 N/A 898 1448 0

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

 N/A 967 1638 1
1000BASE-X/SGMII 2XTBI PCS only

SGMII bridge enabled.

 N/A 1329 2003 2

1000BASE-X.

 N/A 1267 1917 2
10/100/1000 Mb Ethernet MAC with 1000BASEX/SGMII 2XTBI PCS

All MAC options enabled.

SGMII bridge enabled.

PMA block (GXB).

 2048x32 5415 7882 22

All MAC options enabled.

SGMII bridge enabled.

PMA block (FGT).

 2048x32 5213 7279 21
Table 6.  Resource Utilization for Triple-Speed Ethernet in Intel® Stratix® 10 DevicesThe following estimates are obtained by targeting the Intel® Stratix® 10 device as indicated below.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

Intel® Stratix® 10 (1SG280HN3F43E3VG) Device with Speed Grade -3
10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

 2048x32 4055 5398 21
2048x8 3831 5139 16
10/100 Mbps Small MAC

MII.

Full- and half-duplex only.

 2048x32 1460 2078 11
1000 Mbps Small MAC

GMII.

Full-duplex only.

 2048x32 1158 1838 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

 N/A 901 1333 0

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

 N/A 945 1500 0
Intel® Stratix® 10 (1ST280EY3F55E3VG) Device with Speed Grade -3
1000BASE-X/SGMII 2XTBI PCS only SGMII bridge enabled. N/A 1306 1609 2
1000BASE-X N/A 1246 1543 2
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS

All MAC options enabled.

SGMII bridge enabled.

PMA block (GXB).

 2048x32 5292 7244 22
Table 7.  Resource Utilization for Triple-Speed Ethernet for Intel® Arria® 10 DevicesThe following estimates are obtained by targeting the Intel® Arria® 10 GX (10AX115R4F40I3SG) device with speed grade -3.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

 2048x32 3817 5316 22
2048x8 3646 5142 17
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

 2048x32 1354 1986 12
1000 Mbps Small MAC

GMII.

Full-duplex only.

 2048x32 1079 1769 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

 N/A 841 1162 2

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

 N/A 662 995 2

1000BASE-X.

 N/A 641 800 0
Table 8.  Resource Utilization for Triple-Speed Ethernet for Intel® Cyclone® 10 GX DevicesThe following estimates are obtained by targeting the Intel® Cyclone® 10 GX (10CX220YU484I6G) device with speed grade -6.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

 2048x32 3819 5346 22
2048x8 3646 5185 17
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

 2048x32 1358 1992 12
1000 Mbps Small MAC

GMII.

Full-duplex only.

 2048x32 1083 1761 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

 N/A 841 1175 2

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

 N/A 662 992 2

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

 N/A 877 1285 2
Table 9.  Resource Utilization for Triple-Speed Ethernet for Intel® Cyclone® 10 LP DevicesThe following estimates are obtained by targeting the Intel® Cyclone® 10 LP (10CL120YF780I7G) device.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M9K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

 2048x8 6724 4840 17
N/A 5863 4204 8
1000BASE-X/SGMII PCS

1000BASE-X.

SGMII bridge enabled.

 N/A 1628 1133 2
10/100 Mbps Small MAC

MII.

Full and half-duplex only.

 N/A 2416 1933 24
1000 Mbps Small MAC

GMII.

Full-duplex only.

 N/A 1998 1645 24
Table 10.  Resource Utilization for Triple-Speed Ethernet for Intel® MAX® 10 DevicesThe following estimates are obtained by targeting the Intel® MAX® 10 (10M08DAF484C8G) device with speed grade -8.
IP Variation Settings FIFO Buffer Size (Bits) Logic Elements Logic Registers Memory

(M9K)
10/100/1000 Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

 2048x32 6806 4943 30
2048x8 6593 4767 17
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

 2048x32 2650 2117 24
1000 Mbps Small MAC

RGMII

Full-duplex only.

 2048x32 2286 1862 24
Table 11.  Resource Utilization for Triple-Speed Ethernet for Stratix® V Devices The following estimates are obtained by targeting the Stratix® V GX (5SGXMA7N3F45C3) device with speed grade -3.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory 


(M20K Blocks/ MLAB Bits)

10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 1261 2018 11/0

MII.

All MAC options enabled.

 2048x32 1261 2018 11/0
1000 Mbps Small MAC

GMII.

All MAC options enabled.

 2048x32 1227 1959 10/128

RGMII.

All MAC options enabled.

 2048x32 1237 1984 10/128
10/100/1000 Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

 N/A 3137 4298 5/2048
2048x8 3627 4971 10/2048
2048x32 3777 5145 16/2048

MII/GMII.

All MAC options enabled.

 2048x32 3454 4928 16/768

RGMII.

All MAC options enabled.

 2048x32 3466 4933 16/768
1000BASE-X/SGMII PCS 1000BASE-X. N/A 614 786 0/0

1000BASE-X.

SGMII bridge enabled.

 N/A 839 1160 0/480

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

 N/A 857 1250 0/480

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 2203 1991 5/2208

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

The reconfig controller is compiled with this variation.

 N/A 1441 903 4/2048
10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII PCS

All MAC options enabled.

SGMII bridge enabled.

 2048×32 4306 6132 16/1248

Default MAC options.

SGMII bridge enabled.

IEEE 1588v2 feature enabled.

 0 5062 5318 4/1536
Table 12.  Resource Utilization for Triple-Speed Ethernet for Cyclone® V DevicesThe following estimates are obtained by targeting the Cyclone® V GX (5CGXFC7C7F23C8) device with speed grade -8.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M10K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

 2048x32 1425 2299 21
2048x8 1387 2200 9
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

 2048x32 1338 2037 21
1000 Mbps Small MAC

RGMII.

Full-duplex only.

1

2048x32 1120 1829 20
1000BASE-X/SGMII PCS

1000BASE-X.

 N/A 633 846 0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

 N/A 783 1142 2

1000BASE-X.

SGMII bridge enabled.

 N/A 850 1248 2
Table 13.  Resource Utilization for Triple-Speed Ethernet for Stratix® IV DevicesThe following estimates are obtained by targeting the Stratix® IV GX (EP4SGX530NF45C4) device with speed grade -4.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory 


(M9K Blocks/ M144K Blocks/MLAB Bits)

10/100 Mbps Small MAC

MII.

Full- and half-duplex.

 2048x32 1410 2127 12/1/1408

MII.

All MAC options enabled.

 2048x32 1157 1894 12/1/128
1000 Mbps Small MAC

GMII.

All MAC options enabled.

 2048x32 1160 1827 12/1/176

RGMII.

All MAC options enabled.

 2048x32 1170 1861 12/1/176
10/100/1000-Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

 N/A 2721 3395 0/0/3364
2048x8 3201 3977 8/0/3620
2048x32 3345 4425 12/1/3364

MII/GMII.

All MAC options enabled.

 2048x32 3125 3994 12/1/2084

RGMII.

All MAC options enabled.

 2048x32 3133 4021 12/1/2084
1000BASE-X/SGMII PCS 1000BASE-X. N/A 624 661 0/0/0

1000BASE-X.

SGMII bridge enabled.

 N/A 808 986 2/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

 N/A 819 1057 2/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

 N/A 1189 1212 1/0/160
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS

All MAC options enabled.

SGMII bridge enabled.

 2048×32 3971 4950 14/1/2084
Table 14.  Resource Utilization for Triple-Speed Ethernet for Cyclone® IV GX DevicesThe following estimates are obtained by targeting the Cyclone® IV GX (EP4CGX150DF27C7) device with speed grade -7.
IP Variation Settings FIFO Buffer Size (Bits) Logic Elements Logic Registers Memory

(M9K Blocks/ M144K Blocks/ MLAB Bits)

1000 Mbps Small MAC

RGMII

Full-duplex only.

 2048x32 2161 1699 24/0/0
10/100/1000 Mbps Ethernet MAC

MII/GMII

Full- and half-duplex.

 2048x32 5614 3666 31/0/0
1000BASE-X/SGMII PCS 1000BASE-X. N/A 1149 661 0/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

 N/A 2001 1127 2/0/0
Table 15.  Resource Utilization for Triple-Speed Ethernet for Arria® II GX DevicesThe following estimates are obtained by targeting the Arria® II GX (EP2AGX260EF29I3) device with speed grade -3.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M9K Blocks/ M144K Blocks/MLAB Bits)

10/100/1000 Mbps Ethernet MAC

RGMII.

All MAC options enabled.

Full- and half-duplex.

 2048x32 3357 3947 26/0/1828
1000BASE-X/SGMII PCS 1000BASE-X. N/A 624 661 0/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

 N/A 1191 1214 1/0/160
1 This variant is targeting devices with –6 speed grade.
Level Two Title