Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 11/25/2022
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Document Table of Contents
Document Table of Contents x
1. About This IP 2. Getting Started with Intel FPGA IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
1. About This IP x
1.1. Release Information 1.2. Device Family Support 1.3. Features 1.4. 10/100/1000 Ethernet MAC Versus Small MAC 1.5. High-Level Block Diagrams 1.6. Example Applications 1.7. IP Verification 1.8. Performance and Resource Utilization
1.7. IP Verification x
1.7.1. Optical Platform 1.7.2. Copper Platform
2. Getting Started with Intel FPGA IPs x
2.1. Design Walkthrough 2.2. Generated Files
2.1. Design Walkthrough x
2.1.1. Creating a New Intel® Quartus® Prime Project 2.1.2. Generating a Design Example or Simulation Model 2.1.3. Simulating the System 2.1.4. Compiling the Triple-Speed Ethernet Intel® FPGA IP Design 2.1.5. Programming an FPGA Device
2.2. Generated Files x
2.2.1. Design Constraint File No Longer Generated
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. Timestamp Options 3.5. PCS/Transceiver Options
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA 4.3. Intel FPGA IEEE 1588v2 4.4. Deterministic Latency
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.12. PHY Management (MDIO) x
4.1.12.1. MDIO Connection 4.1.12.2. MDIO Frame Format
4.1.13. Connecting MAC to External PHYs x
4.1.13.1. Gigabit Ethernet 4.1.13.2. Programmable 10/100 Ethernet 4.1.13.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
4.2.10. PHY Power-Down x
4.2.10.1. Power-Down in PCS Variations with Embedded PMA
4.3. Intel FPGA IEEE 1588v2 x
4.3.1. IEEE 1588v2 Supported Configurations 4.3.2. IEEE 1588v2 Features 4.3.3. IEEE 1588v2 Architecture 4.3.4. IEEE 1588v2 Transmit Datapath 4.3.5. IEEE 1588v2 Receive Datapath 4.3.6. IEEE 1588v2 Frame Format
4.3.6. IEEE 1588v2 Frame Format x
4.3.6.1. PTP Frame in IEEE 802.3 4.3.6.2. PTP Frame over UDP/IPv4 4.3.6.3. PTP Frame over UDP/IPv6
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.8. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals 6.1.1.10. ECC Status Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals 6.1.3.4. ECC Status Signals
6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) x
6.1.4.1. GMII Clock Signals 6.1.4.2. E-Tile Transceiver Native PHY Signals
6.1.5. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) x
6.1.5.1. F-Tile Transceiver Direct PHY Signals
6.1.8. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals x
6.1.8.1. Deterministic Latency Clock Signals 6.1.8.2. Deterministic Latency Datapath Signals 6.1.8.3. Deterministic Latency Control and Status Interface Signals 6.1.8.4. Deterministic Latency Interface Signals 6.1.8.5. IEEE 1588v2 PCS TX PTP Alignment Interface Signals
6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
6.1.10.1. 1.25 Gbps Serial Interface 6.1.10.2. Transceiver Native PHY Signal 6.1.10.3. Intel® Arria® 10 Transceiver Native PHY Signals 6.1.10.4. SERDES Control Signals 6.1.10.5. Intel LVDS Transmitter and Receiver Soft-CDR I/O Signals
6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
6.1.11.1. IEEE 1588v2 RX Timestamp Signals 6.1.11.2. IEEE 1588v2 TX Timestamp Signals 6.1.11.3. IEEE 1588v2 TX Timestamp Request Signals 6.1.11.4. IEEE 1588v2 TX Insert Control Timestamp Signals 6.1.11.5. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 6.1.11.6. IEEE 1588v2 PCS Phase Measurement Clock Signal 6.1.11.7. IEEE 1588v2 PHY Path Delay Interface Signals
6.1.12. 1000BASE-X/SGMII PCS Signals x
6.1.12.1. PCS Control Interface Signals 6.1.12.2. PCS Reset Signals 6.1.12.3. MII/GMII Clocks and Clock Enablers 6.1.12.4. GMII 6.1.12.5. MII 6.1.12.6. SGMII Status Signals
6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.13.1. Clock Enablers 6.1.13.2. PCS Reset Signals 6.1.13.3. TBI Interface Signals
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive 6.2.9. IEEE 1588v2 Timestamp
7. Design Considerations x
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA x
7.1.1. MAC and PCS With GX Transceivers 7.1.2. MAC and PCS With LVDS Soft-CDR I/O
7.5. Migrating From Old to New User Interface For Existing Designs x
7.5.1. Exposed Ports in the New User Interface
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
10. Software Programming Interface x
10.1. Driver Architecture 10.2. Directory Structure 10.3. PHY Definition 10.4. Using Multiple SG-DMA Descriptors 10.5. Using Jumbo Frames 10.6. API Functions 10.7. Constants
10.6. API Functions x
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About This IP
2. Getting Started with Intel FPGA IPs
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Software Programming Interface
11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters

12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.11.25 22.1 20.0.0 Updated ifInErrors description in Statistics Counters table.
2022.05.30 22.1 20.0.0 Updated Generating a Design Example or Simulation Model topic
  • Added information to clarify support for Intel® Stratix® 10 devices only.
2022.04.04 22.1 20.0.0
  • Updated the following figures:
    • 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, with 1000BASE-X/SGMII PCS Signals.
    • 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile).
    • Clock Distribution in MAC and SGMII PCS with LVDS Configuration - Optimal Case.
    .
  • Removed Intel® Arria® 10 Transceiver Native PHY Signals table in 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals topic.
  • Added FGT transceiver type signals to F-Tile Transceiver Direct PHY Signals table.
  • Updated Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA topic.
  • Added a new Figure: Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (F-Tile).
2021.10.04 21.3 19.5.0
  • Added support for Intel® Agilex™ F-tile devices for the following core variant:
    • 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA
  • Added new topics:
    • 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile)
    • F-tile Transceiver Direct PHY Signals
  • Renamed topic title 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS Signals With Embedded PMA Signals to 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile).
  • Updated the following topics:
    • Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
    • Interface Signals
  • Updated the following tables:
    • Resource Utilization for Triple-Speed Ethernet for Intel® Agilex™ Devices
    • PCS Transmit and Receive Latency
2021.08.23 21.2 19.4.0 Corrected the insert correction of the P2P transparent clock for Delay_Req in Table: Timestamp and Correction Insertion for 1-Step Clock Synchronization.
2021.06.29 21.2 19.4.0 Removed support for NCSim in Table: Simulation Model Files.
2021.06.23 21.2 19.4.0
  • Updated the Features topic.
  • Added information on deterministic latency in Table: Overview of MAC Register Space.
  • Added new topics:
    • Deterministic Latency
    • Deterministic Latency (Dword Offset 0xE1– 0xD3)
    • 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
    • Deterministic Latency Clock Signals
    • Deterministic Latency Datapath Signals
    • Deterministic Latency Control and Status Interface Signals
    • Deterministic Latency Interface Signals
    • IEEE 1588v2 PCS TX PTP Alignment Interface Signals
2021.04.20 20.4 19.4.0
  • Corrected the minimum supported grade with 1588 feature for Intel® Cyclone® 10 GX devices from -I3 to -I5 in Table: Device Family Support for Triple-Speed Ethernet MAC.
  • Corrected the table description for Table: Resource Utilization for Triple-Speed Ethernet for Intel® Cyclone® 10 GX Devices to state that the resource utilization estimates are obtained by targeting the Intel® Cyclone® 10 GX (10CX220YU484I6G) device with speed grade -6.
2021.02.19 20.4 19.4.0
  • Updated the description in Receive of the SGMII Converter topic..
  • Updated the description in Ten-bit Interface section.
  • Updated Table: Resource Utilization for Triple-Speed Ethernet in Intel® Stratix® 10 Devices to include resource utilization for Triple-Speed Ethernet with E-tile transceiver in Intel® Stratix® 10 devices.
  • Removed Table: Resource Utilization for Triple-Speed Ethernet with E-Tile Transceiver in Intel® Stratix® 10 Devices.
  • Updated for latest Intel® branding standards.
2020.12.14 20.4 19.4.0
  • Added support for two new core variants for Intel® Stratix® 10 E-tile devices:
    • 10/100/1000-Mbps Ethernet MAC without internal FIFO buffers with 1000BASE-X/SGMII 2XTBI PCS
    • 10/100/1000-Mbps Ethernet MAC without internal FIFO buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS
  • Added new Figure: 10/100/1000-Mbps Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS.
  • Added a footnote to the settings of 1000-Mbps Small MAC IP variation in Table: Resource Utilization for Triple-Speed Ethernet for Cyclone® V Devices to state that the variant targets devices with –6 speed grade.
  • Added a note to the description of the Interface parameter on the recommended speed grades for Cyclone® V devices in Table: Core Configuration Parameters.
  • Updated Table: Resource Utilization for Triple-Speed Ethernet for Cyclone® V Devices.
  • Added information on Intel® Stratix® 10 GXB PMA Adaptation parameter to Table: PCS/Transceiver Options Parameters.
  • Updated the description in IEEE 1588v2 Supported Configurations.
  • Updated the description for the following signals in Table: IEEE 1588v2 TX Timestamp Interface Signals:
    • tx_egress_timestamp_96b_data_n
    • tx_egress_timestamp_96b_valid
    • tx_egress_timestamp_64b_data
    • tx_egress_timestamp_64b_valid
  • Updated the descriptions for the following signals in Table: IEEE 1588v2 TX Insert Control Timestamp Interface Signals:
    • tx_etstamp_ins_ctrl_residence_time_update
    • tx_etstamp_ins_ctrl_checksum_zero
    • tx_etstamp_ins_ctrl_checksum_correct
  • Updated Sharing PLLs in Devices with LVDS Soft-CDR I/O to include LVDS soft-CDR placement guidelines for Intel® Agilex™ devices.
  • Updated topic title 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS Signals to 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals.
  • Made editorial updates throughout the document.
2020.10.05 19.4 19.4.0
  • Updated the following topic, figures, and table include the LVDS change:
    • Sharing PLLs in Devices with LVDS Soft-CDR I/O
    • Figure: Clock Distribution in MAC and SGMII PCS with LVDS Configuration—Optimal Case
    • Figure: Clock Distribution in MAC and 1000BASE-X PCS with LVDS Configuration—Optimal Case
    • Table: Core Configuration Parameters
  • Added a note to Simulation Model Files.
  • Updated Length Checking with information about jumbo frame.
  • Updated Table: Core Configuration Parameters to include the information of the FPGA device with E-tile transceivers for Core Variation and Transceiver type.
  • Updated Table: MAC Control Interface Signals to include more details about reg_busy.
  • Made editorial updates throughout the document.
2020.02.27 19.4 19.4.0
  • Updated the Payload Pad Removal topic.
2019.12.16 19.4 19.4.0
  • Added support for Intel® Agilex™ devices.
  • Added new section—Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA.
  • Added a foot note to the Minimum Speed Grade with 1588 Feature value of the Intel® Stratix® 10 (E-tile) in Table: Device Family Support for Triple-Speed Ethernet MAC.
  • Updated the Features topic.
  • Updated the Performance and Resource Utilization topic:
    • Added new Table: Resource Utilization for Triple-Speed Ethernet for Intel® Agilex™ Devices.
    • Update Table: Resource Utilization for Triple-Speed Ethernet in Intel® Stratix® 10 Devices.
    • Updated Table: Resource Utilization for Triple-Speed Ethernet with E-Tile Transceiver in Intel® Stratix® 10 Devices.
    • Updated Table: Resource Utilization for Triple-Speed Ethernet for Intel® Arria® 10 Devices.
    • Updated Table: Resource Utilization for Triple-Speed Ethernet for Intel® Cyclone® 10 GX Devices.
  • Remove the note in the Generating a Design Example or Simulation Model topic.
  • Updated the description of the Transceiver type parameter in Table: Core Configuration Parameters.
  • Updated the parameter name Enable Stratix 10 transceiver dynamic reconfiguration to Enable E-tile transceiver dynamic reconfiguration in Table: PCS/Transceiver Options Parameters.
  • Added a new Topic— Intel LVDS Transmitter and Receiver Soft-CDR I/O Signals.
  • Updated the description in the Receive FIFO Buffer and Local Device Congestion topic.
  • Updated Table: PCS Transmit and Receive Latency to include latency information for the following Intel® Stratix® 10 E-tile configuration:
    • 10-Mbps SGMII 2XTBI PCS
    • 100-Mbps SGMII 2XTBI PCS
    • 10-Mbps SGMII 2XTBI PCS with GXB
    • 100-Mbps SGMII 2XTBI PCS with GXB
  • Updated the description in the 1000BASE-X/SGMII PCS With Optional Embedded PMA topic.
  • Updated the FPGA IEEE 1588v2 Feature topic.
  • Updated the GMII Clock Signals topic.
  • Updated the following figures:
    • Updated figure and figure title 10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA to 10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS with PMA.
    • Updated figure and figure title 1000BASE-X/SGMII 2XTBI PCS with Optional PMA to 1000BASE-X/SGMII 2XTBI PCS.
    • Clock Distribution in MAC and SGMII PCS with GXB Configuration—Optimal Case
    • Clock Distribution in MAC and SGMII PCS with LVDS Configuration—Optimal Case.
    • Power-Down.
    • Corrected figure title PTP Frame in IEEE 8002.3 to PTP Frame in IEEE 802.3
    • Updated Figure: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers Signals.
    • Updated Figure: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers Signals.
    • Updated Figure: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, with 1000BASE-X/SGMII PCS Signals.
    • Updated Figure: 0/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS Signals With Embedded PMA Signals.
    • Updated Figure: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with 1000BASE-X/SGMII PCS Signals.
    • Updated Figure: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS With Embedded PMA Signals.
    • Updated Figure: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers, with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals.
    • Updated Figure: 1000BASE-X/SGMII PCS Function Signals.
    • Updated Figure: 1000BASE-X/SGMII 2XTBI PCS Function Signals.
    • Updated Figure: 1000BASE-X/SGMII PCS Function and PMA Signals.
    • Updated Figure: Reset Distribution in MAC with PCS and Embedded PMA.
  • Updated the Table: GMII/RGMII/MII Clock Signals in the 10/100/1000 Ethernet MAC Signals section to remove tx_clkena and rx_clkena signals.
  • Added a new topic for the for the 10/100/1000 Ethernet MAC Signals section—Clock Enabler Signals.
  • Updated Table: Clock Signals Visible at Top-Level Design:
    • Updated the table description.
    • Added footnotes for ff_tx_clk and ff_rx_clk.
  • Updated the note in the Creating Clock Constraints topic to state that the derive_pll_clocks command is not supported in Intel® Stratix® 10 devices because all PLL clocks are automatically generated by the SDC files generated alongside the PLL IP.
  • Corrected the term gbx_pwrdn_in to gxb_pwrdn_in.
  • Updated the term "MegaWizard Plug-In Manager" to "IP Catalog".
  • Renamed topic title Intel Stratix 10 E-tile Transceiver Native PHY Signals to E-tile Transceiver Native PHY Signals.
  • Updated for latest Intel® branding standards.
2019.11.01 19.3 19.3.0
  • Corrected the minimum speed grade with 1588 feature for Intel® Stratix® 10 E-tile devices from "-I3" to "Not supported".
  • Updated the descriptions in the following topics:
    • Features
    • Intel® FPGA IP IEEE 1588v2 Feature
  • Updated Table: IEEE 1588v2 Feature LVDS I/O Delay—Hardware.
2019.09.30 19.3 19.3.0
  • Updated Table: Device Family Support for Triple-Speed Ethernet MAC.
  • Updated Table: Simulation Model Files.
  • Updated the notes for Figure: Clock Distribution in MAC and 1000BASE-X PCS with LVDS Configuration—Optimal Case.
2019.07.24 19.2 19.2.0
  • Added support for two new core variants for Intel® Stratix® 10 E-tile devices:
    • 10/100/1000-Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
    • 1000BASE-X/SGMII 2XTBI PCS
  • Added a new Topic: GMII Converter.
  • Added a new Table: Resource Utilization for Triple-Speed Ethernet with E-tile Transceiver in Intel® Stratix® 10 Devices.
  • Updated Table: PCS/Transceiver Options Parameters:
    • Added Intel® Stratix® 10 GXB Transceiver Options parameter to the table.
    • Added a second note to clarify that the Transceiver Options and Series V GXB Transceiver Options parameters are not available in the Triple-Speed Ethernet Intel® FPGA IP parameter editor interface of the Intel® Quartus® Prime Pro Edition software version 19.2 onwards. These options are only present in the Intel® Quartus® Prime Standard Edition software.
  • Updated Table: PCS Transmit and Receive Latency to include latency information for Intel® Stratix® 10 E-tile configuration.
  • Added a note to the MAC Configuration Register Space topic.
  • Updated Table: PCS Control Register Bit Descriptions to update the descriptions for COLLISION_TEST and DUPLEX_MODE.
  • Updated c0 clock frequency from 110 MHz to 100 MHz and added a note of recommended clock frequencies for different FIFO widths for ff_tx_clk and ff_rx_clk signals in Figure: Triple-Speed Ethernet Timing Constraint Example.
  • Updated recommended clock frequencies for ff_tx_clk and ff_rx_clk signals in Table: Recommended Clock Input Frequency For Each IP Core Variant.
  • Updated Table: Statistics Counters to change the ifOutDiscards register to Reserved.
  • Restructured the document.
2019.03.29 17.1 17.1 Updated the note in the MAC Error Correction Code (ECC) topic to state that the error correction code (ECC) feature is applicable to Arria® V GZ, Stratix® V, and Intel® Arria® 10 devices.
2019.02.21 17.1 17.1 Updated the project directory path for VHDL design in the Simulate the IP Core topic.
2019.01.28 17.1 17.1 Added notes to the Multicast Address Resolution topic.
2018.11.28 17.1 17.1 Updated Table: Clock Signals Visible at Top-Level Design to add notes for ref_clk under MAC Only and MAC+PCS configurations.
2018.08.01 17.1 17.1
  • Renamed the document as Triple-Speed Ethernet Intel FPGA IP Core User Guide.
  • Updated the description of the MAC Transmit Datapath topic.
  • Updated the "Command_Config Register Field Descriptions" and "PCS Configuration Registers" tables: Added HW reset values to all registers.
  • Updated Table: Transmit and Receive Nominal Latency.
  • Updated Table: Statistics Counters to update the descriptions for aOctetsReceivedOK, ifOutErrors, ifOutUcastPkts, ifOutMulticastPkts, and ifOutBroadcastPkts registers.
  • Updated for latest Intel branding standards.
Date Version Changes
November 2017 2017.11.06
  • Rebranded as Intel.
  • Renamed the document as Intel FPGA Triple-Speed Ethernet IP Core User Guide.
  • Added support for the Intel Stratix 10, Intel Cyclone 10 GX, and and Intel Cyclone 10 LP device families.
  • Updated the description of the About This IP Core topic.
  • Added "Intel FPGA IP Core Device Support Levels" table to the Device Family Support topic.
  • Removed the Definition: Device Support Level topic.
  • Updated the "Intel Arria 10 Resource Utilization", "Cyclone V Resource Utilization" table: Updated the IP core name from 1000BASE-X/SGMII PCS with PMA to 1000BASE-X/SGMII PCS.
  • Updated the Generating a Design Example or Simulation Model topic:
    • Added a note to clarify that the Generate Example Design option only generates the design for functional simulation.
    • Added a note to clarify that the dynamically generated design example for functional simulation is available only in Intel Arria 10, Intel Cyclone GX, and Intel Stratix 10 devices.
  • Updated the "Recommended Quartus Pin Assignments" table: Updated the Design Pin information for GLOBAL_SIGNAL pin assignment.
  • Updated the "Core Configuration Parameters" table:
    • Added a note to the description of Interface parameter to clarify that RGMII interface is not supported in Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 devices from Intel Quartus Prime software version 17.1 onwards.
    • Added a note to the description of Number of ports to clarify that the number of ports supported for Triple-Speed Ethernet designs targeting Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices is 8 in Intel Quartus Prime software version 17.1 onwards.
    • Added a note to the description of Transceiver type parameter to clarify on the performance risk when using Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel Arria 10 devices for Intel Quartus Prime software versions 17.0.2 and earlier.
  • Updated Figure: Hardware Multicast Address Resolution Engine
  • Updated the "PCS Transmit and Receive Latency" table:
    • Added PCS transmit and receive latency for Intel Stratix 10 and Intel Cyclone 10 GX devices.
    • Added a footnote under the Latency (Clock Cycles) column to clarify that the latency numbers are from simulation.
  • Updated the description in the CRC Checking topic.
  • Updated the Configuration Register Space section:
    • Updated the "IEEE 1588v2 Feature PMA Delay—Hardware" table to include digital delay information for Intel Arria 10 devices.
    • Updated the "IEEE 1588v2 Feature LVDS I/O Delay—Hardware" table to include digital delay information for Intel Arria 10 and Intel Stratix 10 devices.
  • Updated the description of the MAC and PCS With LVDS Soft-CDR I/O topic: Added a note to clarify on the performance risk when using Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel Arria 10 devices for Intel Quartus Prime software versions 17.0.2 and earlier.
  • Added a note to the Sharing PLLs in Devices with LVDS Soft-CDR I/O topic.
  • Updated the Creating Clock Constraints topic: Added a note to clarify that the derive_pll_clocks command is not supported in Intel Stratix 10 devices.
  • Made editorial updates throughout the document.
March 2017 2017.03.08
  • Updated the note below Figure 6-5 in the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals topic.
  • Updated the Arria 10 and Cyclone V Resource Utilization tables to include information about 10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS MegaCore Function.
  • Updated the link in the Related Information section for the Altera IEEE 1588v2 Features topic.
  • Editorial fix to the notes in Figures 6-5, 6-6, 6-7, and 7-2.
January 2017 2017.01.05
  • Added ordering code IP-TRIETHERNETF for IEEE 1588v2 and product ID(s) 00BD and 0104 for Triple-Speed Ethernet and IEEE 1588v2.
January 2017 2017.01.05 Corrected typo in the Configuration Register Space topic.
October 2016 2016.10.31
  • Corrected the Device Family Support topic to include all supported devices, including devices that do not have the 1588 feature support.
  • Removed mention of read_timeout in the topic about MAC reset.
  • Updated the description of DISABLE_READ_TIMEOUT in the topic about the command_config register.
  • Removed read_timeout and disable_read_timeout registers from the table that lists the PCS configuration registers.
May 2016 2016.05.02
  • Updated the Device Family Support topic.
  • Updated the Performance and Resource Utilization topic.
  • Updated the Release Information topic.
  • Removed the Design Example topic and the appendices that described the design components, Time-of-Day (ToD) Clock, ToD Synchronizer, and Packet Classifier. Added a link to the application note for the design example.
  • Added the Document Archives topic that lists documents for the past releases.
  • Removed the PMA and LVDS I/O Delay—Simulation Model tables from the IEEE 1588v2 Feature PMA Delay topic because simulation data is not deterministic.
November 2015 2015.11.02
  • ToD Clock chapter:
    • Updated the device family support.
    • Added a new parameter—PERIOD_CLOCK_FREQUENCY.
    • Updated the CSR description for SecondsH, SecondsL, NanoSec, Period, AdjustPeriod, DriftAdjust, and DriftAdjustRate.
  • ToD Synchronizer chapter:
    • Updated the device family support.
    • Changed the frequency range to 390.625 MHz (from 312.5 MHz)
    • Added a new table—"Sampling Clock Frequency According to the Selected Parameter Settings".
    • Updated the "Settings to Achieve the Recommended Factors for Stratix V PLL" table with more sampling clock factors.
    • Updated the parameter value of SYNC_MODE to "Between 0 to 15" (from "Between 0 to 6").
    • Added a new parameter—SAMPLE_SIZE.
  • Updated the description for tx_serial_clk to state that the clock frequency is 1250 MHz.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.15
  • Added a new parameter, , in the Core Configuration Parameters table.
  • Added description for new signals—tx_clkena, rx_clkena, and led_panel_link.
  • Added Qsys-equivalent signal names for the following signals:Use clock enable for MAC
    • control_port_clock_connection: clk
    • pcs_mac_tx_clock_connection: tx_clk
    • pcs_mac_rx_clock_connection: rx_clk
    • receive_clock_connection: ff_rx_clk
    • transmit_clock_connection: ff_tx_clk
  • Revised the Command_config register field descriptions for bits 0, 1, and 13.
  • Corrected the Command_config register setting for Enable MAC Transmit and Receive Datapath register initialization sequence from 0x00802223 to 0x00800223.
  • Corrected the bit width for pkt_class_dataUse clock enable signal in the following timing diagrams:
    • Receive Operation—MAC Without Internal FIFO Buffers.
    • Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers.
  • Updated the following sections to indicate that the reconfiguration signals are not present in variations targeting Arria 10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
    • note in 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
    • SERDES control signals description in SERDES Control Signals.
    • note in 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
    • Sharing Transceiver Quads
  • Updated the description for Extended Statistics Counters (0x3C – 0x3E) to state the specific order for reading counters.
  • Removed "10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS" configuration from the list of supported configurations in IEEE 1588v2 feature.
  • Added a new topic—Using ToD Clock SecondsH, SecondsL, and NanoSecRegisters.
June 2014 14.0
  • Added a link to the Altera website that provides the latest device support information for Altera IP.
  • Added a note in PCS/Transceiver Options—You must configure the Arria 10 Transceiver ATX PLL output clock frequency to 1250.0 MHz when using the Arria 10 Transceiver Native PHY with the Triple-Speed Ethernet IP core.
  • Added MAC Error Correction Code (ECC) section.
  • Added new support configuration for IEEE 1588v2 feature.
  • Updated the tx_period and rx_period register bits in IEEE 1588v2 Feature (Dword Offset 0xD0 - 0xD6).
  • Updated the timing adjustment for the IEEE 1588v2 feature PMA delay in IEEE 1588v2 Feature PMA Delay.
  • Revised the control interface signal names to reg_rd, reg_data_in, reg_wr, reg_busy, and reg_addr in MAC Control Interface.
  • Added ECC status signals in ECC Status Signals and ECC Status Signals .
  • Added Arria 10 Transceiver Native PHY signals in Transceiver Native PHY Signals.
  • Added Transceiver Native PHY signal in Transceiver Native PHY Signals.
  • Updated the following the signal diagrams:
    • 10/100/1000 Ethernet MAC Signals
    • 1000BASE-X/SGMII PCS Function Signals
    • 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
    • 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers, with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals
  • Added IEEE 1588v2 feature PHY path delay interface signals inIEEE 1588v2 PHY Path Delay Interface Signals .
  • Updated the Period and AdjustPeriod register bits in ToD Clock Configuration Register Space.
  • Added two new conditions that the ToD synchronizer module supports in ToD Synchronizer chapter.
  • Added three new recommended sampling clock frequencies in ToD Synchronizer chapter.
  • Added a new setting of 32/63 in ToD Synchronizer Block.
  • Updated the SYNC_MODE parameter value and description in ToD Synchronizer Parameter Settings.
December 2013 13.1
  • Added support for Arria 10 device.
  • Added device family support list for IEEE 1588v2 variant.
  • Updated the PCS/Transceiver options parameters in PCS/Transceiver Options .
  • Updated the bit order in SGMII MAC Mode Auto Negotiation , SGMII PHY Mode Auto Negotiation and If Mode Register (Word Offset 0x14).
  • Added information on how to view all the signal names when implementing the IP in Qsys in Interface Signals.
  • Added a section about exposed ports in the new user interface in Design Considerations.
May 2013 13.0
  • Updated the MegaWizard Plug-In Manager flow in Getting Started with Altera IP Cores.
  • Added information about generating a design example and simulation testbench in Generating a Design Example or Simulation Model.
  • Updated the list of Quartus II generated files.
  • Added information about the recommended pin assignments in Design Constraint File No Longer Generated.
  • Updated the MegaCore parameter names and description in Parameter Settings.
  • Updated the IEEE 1588v2 feature list in Functional Descriptions .
  • Updated the SGMII auto-negotiation description in Functional Descriptions.
  • Added information about the IEEE 1588v2 feature PMA delay in IEEE 1588v2 Feature PMA Delay.
  • Updated the Multiport Ethernet MAC with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals.
  • Updated the IEEE 1588v2 timestamp signal names.
  • Added timing diagrams for IEEE 1588v2 timestamp signals.
  • Added a section about migrating existing design to the Quartus II software new MegaCore user interface in Design Considerations.
  • Updated Timing Constraints chapter, to describe the new timing constraint files and the recommended clock input frequency for each MegaCore Function variant.
  • Added information about the simulation model files generated using IEEE simulation encryption in Simulation Model Files.
  • Updated the jumbo frames file directory in Using Jumbo Frames.
  • Updated the ToD configuration parameters in ToD Clock Parameter Setting and ToD interface signals, ToD Clock Avalon-ST Transmit Interface Signals and ToD Clock Avalon-MM Control Interface Signals.
  • Added information to describe the ToD’s drift adjustment in the Adjusting ToD Clock Drift.
  • Added ToD Synchronizer and Packet Classifier chapters.
  • Removed SOPC Builder information.
January 2013 12.1
  • Added Altera IEEE 1588v2 Feature section in Chapter 4.
  • Added information for the following GUI parameters: Enable timestamping, Enable PTP 1-step clock, and Timestamp fingerprint width in “Timestamp Options”.
  • Added MAC registers with IEEE 1588v2 feature.
  • Added IEEE 1588v2 feature signals tables.
  • Added Triple-Speed Ethernet with IEEE 1588v2 Design Example section.
  • Added Time-of-Day Clock section.
June 2012 12.0
  • Added support for Cyclone V.
  • Updated the Congestion and Flow Control section in Chapter 4.
  • Added Register Initialization section in Chapter 5.
  • Added holdoff_quant register description.
  • Added UNIDIRECTIONAL_ENABLE bit description.
  • Revised and moved the section on Timing Constraint to a new chapter.
  • Added information about how to customize the SDC file in Chapter 8.
  • Added Pause Frame Generation section.
November 2011 11.1
  • Added support for Arria V.
  • Revised the Device Family Support section in Chapter 1.
  • Added disable_read_timeout and read_timeout registers at address 0x15 and 0x16.
June 2011 11.0
  • Updated support for Cyclone IV GX, Cyclone III LS, Aria II GZ, HardCopy IV GX/E and HardCopy III E devices.
  • Revised Performance and Resource Utilization section in Chapter 1.
  • Updated Chapter 3 to include Qsys System Integration Tool Design Flow.
  • Added Transmit and Receive Latencies section in Chapter 4.
  • Updated all MAC register address to dbyte addressing.
December 2010 10.1
  • Added support for Arria II GZ.
  • Added a new parameter, Starting Channel Number.
  • Streamlined the contents and document organization.
August 2010 10.0
  • Added support for Stratix V.
  • Revised the nomenclature of device support types.
  • Added chapter 5, Design Considerations. Moved the Clock Distribution section to this chapter and renamed it to Optimizing Clock Resources in Multiport MAC and PCS with Embedded PMA. Added sections on PLL Sharing and Transceiver Quad Sharing.
  • Updated the description of Enable transceiver dynamic reconfiguration.
November 2009 9.1
  • Added support for Cyclone IV, Hardcopy III, and Hardcopy IV, and updated support for Hardcopy II to full.
  • Updated chapter 1 to include a feature comparison between 10/100/1000 Ethernet MAC and small MAC.
  • Updated chapter 4 to revise the 10/100/1000 Ethernet MAC description, Length checking, Reset, and Control Interface sections.
March 2009 9.0
  • Added support for Arria II GX.
  • Updated chapter 3 to include a new parameter that enables wider statistics counters.
  • Updated chapter 4 to reflect support for different speed in multiport MACs and gated clocks elimination.
  • Updated chapter 6 to reflect enhancements made on the device drivers.
November 2008 8.1
  • Updated Chapters 3 and 4 to add description on dynamic reconfiguration.
  • Updated Chapter 6 to include a procedure to add unsupported PHYs.
May 2008 8.0
  • Revised the performance tables and device support.
  • Updated Chapters 3 and 4 to include information on MAC with multi ports and without internal FIFOs.
  • Revised the clock distribution section in Chapter 4.
  • Reorganized Chapter 5 to remove redundant information and to include the new testbench architecture.
  • Updated Chapter 6 to include new public APIs.
October 2007 7.2
  • Updated Chapter 1 to reflect new device support.
  • Updated Chapters 3 and 4 to include information on Small MAC.
May 2007 7.1
  • Added Chapters 2, 3, 5 and 6.
  • Updated contents to reflect changes and enhancements in the current version.
March 2007 7.0 Updated signal names and description.
December 2006 6.1
  • Global terminology changes: 1000BASE-X PCS/SGMII to 1000BASE-X/SGMII PCS, host side or client side to internal system side, HD to half-duplex.
  • Initial release of document on Web.
December 2006 6.1 Initial release of document on DVD.
Level Two Title