Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Examples Packet Mode Transfer Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

4.5.3.2. Receive User Data Interface Examples

The Interlaken Look-aside mode only supports packet mode data transfer. The following example illustrate how to use Interlaken Look-aside RX user data interface during a normal packet transfer:

Packet Mode Transfer Example

This example illustrates the expected behavior of the Interlaken Look-aside application interface receive signals during a packet transfer in packet mode.
Figure 25. Packet Transfer on Receive InterfaceThe following figure illustrates two packet transfer of 120 bytes and 49 bytes on the transmit interface with number of lanes is equal to eight and TX_CREDIT_LATENCY is equal to four.
From cycle 0 to cycle 4, there is no valid data drop by the IP as irx_valid deassert.

In cycle 5, the IP core asserts irx_valid, and all of irx_idle bits indicating that irx_dout_words carry idle control words.

In cycle 6, the IP deasserts irx_valid signal again indicating all of other signals are invalid.

In cycle 7, the IP core asserts irx_valid with irx_idle[7:0] is equal to 8'h0, which indicates irx_sop, irx_eopbits, and irx_dout_words carry valid data. The assertion of itx_sop[7] indicates the start of packet at the leftmost words. Corresponding irx_chan[7] indicates the channel associated with this data packet following this control word. With irx_eopbits is 0x0, irx_dout_words represents the actual data words of packet.

In cycle 8, the assertion of irx_eopbits[3] terminates the transfer of data, which happens on the rightmost words. All data words on irx_dout_words[511:0] are the last words of the packet. irx_eopbits[3:0]== 4'b1000 indicates all 8 bytes of the rightmost data word are valid.

In cycle 9, IP core deasserts irx_valid signal again indicating that all of the other signals are not valid.

In cycle 10, IP core flushes new packet with assertion of irx_sop[7] and irx_valid. The packet terminated in the same cycle as well with assertion of irx_eopbits[3]. The rx_eopbits[3:0]== 4’b1001 indicates only 1 byte of the rightmost words is valid. In this cycle, IP core outputs 49 bytes of data which is accessible from irx_dout_words[447:56].

In cycle 11, IP core deasserts irx_valid signal again indicating that all of other signals are not valid.

In cycle 12, IP core asserts irx_valid and all of irx_idle bits indicating that irx_dout_words carry idle control words.

This signal behavior correctly transfers first data packet as follows:
  • In cycle 7, the IP core outputs burst control word and 56 bytes of valid data (data 1).
  • In cycle 8, the IP core output 64 bytes of valid data (data 2).

The total packet length for the first packet is 56+64= 120 bytes.

This signal behavior correctly transfers second data packet as follows:
  • In cycle 10, the IP core outputs burst control word and 49 bytes of valid data (data 3).

The total packet length for the first packet is 49 bytes.

Level Two Title