Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Examples
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. The number of ALMs and logic registers are rounded up to the nearest 100. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.   Intel® Stratix® 10 FPGA Resource Utilization in Interlaken ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 20.3.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Stratix® 10 L-tile 4 6.25 11500 22700 4400 32
12.5 11900 24600 4000 32
25.28 12000 24900 4400 32
25.78 12000 24800 4200 32
25.78125 12000 25000 4200 32
8 12.5 23000 50400 7200 56
10 12.5 29000 64300 8300 65
12 10.3125 24100 51300 7600 56
12.5 24000 50800 8100 56
Intel® Stratix® 10 H-tile 4 6.25 11500 22900 4200 32
12.5 12200 24900 4200 32
25.28 12400 25500 4000 32
25.78 12400 25500 4200 32
25.78125 12400 25400 4100 32
6 25.28 23800 50700 7300 56
25.78 23800 50500 7300 56
25.78125 23700 50400 7700 56
8 12.5 23800 51000 7300 56
25.28 24200 52000 6400 56
25.78 24300 51200 6800 56
25.78125 24100 52400 6300 56
10 12.5 29000 64600 8000 65
25.28 35700 84600 7500 104
25.78 35700 81100 7600 104
25.78125 35700 80300 8700 104
12 10.3125 25200 52700 7400 56
12.5 24200 51000 7900 56
25.28 38600 88000 9800 104
25.78 38700 87400 10400 104
25.78125 38600 88000 9200 104
Intel® Stratix® 10 E-tile (NRZ) 4 6.25 17300 33500 5600 32
12.5 17300 33500 5700 32
25.28 17500 33600 5800 32
25.78 17500 33400 5800 32
25.78125 17500 33200 5900 32
6 25.28 31400 63000 10300 56
25.78 31400 63300 9900 56
25.78125 31400 63500 10400 56
8 12.5 34000 68200 10400 56
25.28 34500 68400 40400 56
25.78 34500 68600 9700 56
25.78125 34500 67900 10500 56
10 12.5 42700 86700 12000 65
25.28 48500 101400 12500 104
25.78 48500 100600 13200 104
25.78125 48500 100800 12800 104
12 10.3125 51800 104900 14200 77
12.5 49700 102600 14300 89
25.28 54000 112700 15200 104
25.78 54000 112000 15650 104
25.78125 54000 112200 15200 104
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 67000 137600 17900 104
Table 5.   Intel® Agilex™ FPGA Resource Utilization in Interlaken ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 20.3:
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ E-tile (NRZ) 4 6.25 17700 33500 7700 32
12.5 17500 33400 7800 32
25.28 17800 34000 8000 32
25.78 17700 34000 7800 32
25.78125 17900 34000 8000 32
6 25.28 31800 63700 13700 56
25.78 31700 63700 13600 56
25.78125 31700 63500 13800 56
8 12.5 34200 68200 13300 56
25.28 34600 68900 14100 56
25.78 34600 69000 13900 56
25.78125 34600 69100 13900 56
10 12.5 43200 86600 16000 65
25.28 48600 120100 17600 104
25.78 48600 102000 18000 104
25.78125 48500 101600 18000 104
12 10.3125 52000 105100 18000 77
12.5 50000 102700 18300 89
25.28 54200 113800 20600 104
25.78 54100 113300 20500 104
25.78125 54300 113800 20700 104
Intel® Agilex™ E-tile (PAM4) 12 26.5625 67700 137400 26000 104
Table 6.   Intel® Stratix® 10 E-tile Resource Utilization Numbers in Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 20.3:
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20 Blocks
Primary Secondary
Intel® Stratix® 10 E-tile ( NRZ) 4 6.25 11900 19700 3300 4
12.5 11800 19500 3400 4
25.28 11900 19600 3300 4
25.78 11800 19600 3300 4
25.78125 11900 19600 3300 4
6 25.28 17600 29300 4700 4
25.78 17400 29000 4800 4
25.78125 17500 29000 4800 4
8 12.5 23200 39300 6300 4
25.28 23400 39100 6100 4
25.78 23500 39200 6100 4
25.78125 23400 39000 6300 4
10 12.5 29600 51000 7900 4
25.28 29600 50000 7900 4
25.78 29700 50000 7900 4
25.78125 29900 50500 7600 4
12 10.3125 35700 62600 9000 4
12.5 35800 62200 9200 4
25.28 35800 61500 8800 4
25.78 36000 61000 8900 4
25.78125 35900 61000 9000 4
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 49400 86500 11800 4
Table 7.   Intel® Agilex™ E-tile Resource Utilization Numbers in Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 20.3:
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20 Blocks
Primary Secondary
Intel® Agilex™ E-tile (NRZ) 4 6.25 11800 19000 4600 4
12.5 11800 19400 4300 4
25.28 11900 19500 4600 4
25.78 11700 19300 4500 4
25.78125 11800 19300 4600 4
6 25.28 17200 28500 6900 4
25.78 17100 28500 6700 4
25.78125 17200 28600 6900 4
8 12.5 23400 39200 8400 4
25.28 23500 39000 9000 4
25.78 23200 38800 9000 4
25.78125 23400 39000 8800 4
10 12.5 29500 50000 10700 4
25.28 29900 50100 11700 4
25.78 29700 49900 11200 4
25.78125 29800 50000 11400 4
12 10.3125 35700 61200 12600 4
12.5 35900 61200 12600 4
25.28 35800 60900 13000 4
25.78 35900 60600 13100 4
25.78125 35800 60800 13500 4
Intel® Agilex™ E-tile ( PAM4) 12 26.5625 49200 86000 17200 4
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