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1. About the Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide
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3.6. Link Debugging Sequence
The Serial Lite IV IP provides a link debugging sequence for TX and RX that you can use when debugging your design.
Figure 17. TX Link Debugging Flowchart
Signal | Location | Description |
---|---|---|
tx_link_up | Top-level TX signal | The IP asserts this signal to indicate that the initialization sequence is complete and the IP is ready to transmit the data. |
tx_pll_locked | Top-level PHY signal | This active-high signal indicates that the transceivers are locked to the reference clock. |
phy_tx_lanes_stable | Top-level PHY signal | The IP asserts this signal when TX datapath is ready to send data. |
phy_ehip_ready[(n*2)-1:0] | Top-level PHY signal | The IP asserts this signal after the tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n signals deassert to indicate that the custom PCS has completed internal initialization and is ready for transmission. |
Figure 18. RX Link Debugging Flowchart
Signal | Location | Description |
---|---|---|
rx_link_up | Top-level RX signal | The IP asserts this signal to indicate that the initialization sequence is complete, and the IP is ready to receive data. |
phy_rx_pcs_ready[(n*2)-1:0] | Top-level PHY signal | The IP asserts this signal when RX datapath is ready to receive data. |
phy_rx_block_lock[(n*2)-1:0] | Top-level PHY signal | The IP asserts this signal to indicate the 66b block alignment has completed for the lanes. |