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1. About the Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide
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2.3. Generating the Design
You can use the IP parameter editor in the Intel® Quartus® Prime Pro Edition software to generate the design example.
Figure 3. Generating the Design Flow
To generate the design example from the IP parameter editor:
- In the Tools > IP Catalog, locate and select Serial Lite IV Intel® FPGA IP . The IP parameter editor appears.
- Specify the parameters for your design.
- Click the Generate Example Design button.
The software generates all design files in the sub-directories. You need these files to run simulation, compilation, and hardware testing.
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