Low Latency 100G Ethernet Design Example User Guide

ID 683371
Date 11/08/2017
Public

2.4.2. CAUI-4 IP Core Variation

The design example for CAUI-4 variations configures two ATX PLLs and connects the output tx_serial_clk signal of each ATX PLL to two of the four IP core transceiver channels. The required ATX PLL output frequency only supports a fanout of two. If this arrangement is not available for your design, you can use additional external ATX and CMU PLLs to generate and distribute the tx_serial_clk signals for the individual channels.
Figure 9. CAUI-4 IP Core Variation Testbench
The simulation testbench instantiates the IP core and necessary PLLs. It interfaces directly with the Avalon-ST port to provide basic packet sending and receiving. The TX and RX lanes can be connected together to provide loopback testing capabilities.