1.4. Simulating the Design
Figure 6. Procedure
File Names |
Description |
---|---|
Testbench and Simulation Files |
|
basic_avl_tb_top.v | Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
Testbench Scripts |
|
run_vsim.do | The ModelSim script to run the testbench. |
run_vcs.sh | The Synopsys VCS script to run the testbench. |
run_ncsim.sh | The Cadence NCSim script to run the testbench. |
Follow these steps to simulate the testbench:
- Change to the testbench simulation directory <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
- Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
Table 2. Steps to Simulate the Testbench Simulator Instructions ModelSim In the command line, type vsim -do run_vsim.do If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do
Note: The ModelSim® - Intel FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim SE.NCSim In the command line, type sh run_ncsim.sh VCS In the command line, type sh run_vcs.sh