Low Latency 100G Ethernet Design Example User Guide

ID 683371
Date 11/08/2017
Public

2.1. Features

DUT features:

  • Standard CAUI external interface consisting of FPGA hard serial transceiver lanes operating at 10.3125 Gbps, or the CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
  • Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
  • The design example requires that you specify the Avalon-ST client interface. Avalon-ST data path interface connects to client logic with the start of frame in the most significant byte (MSB). Interface has data width 512 bits.
  • RX CRC checking and error reporting.
  • TX error insertion capability supports test and debug.
  • Hardware and software reset control.