SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

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ID 683368
Date 12/09/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel® FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

2.4. Clocking Scheme Signals

The table lists the clocking scheme signals for the SDI II Intel® FPGA IP core design examples.
Table 15.  Clocking Scheme Signals
Clock Signal Name in Design Description
TX PLL Refclock tx_pll_refclk
TX PLL reference clock, of any frequency that is divisible by the transceiver for that data rate. You must connect this clock to a dedicated transceiver reference clock pin.
Note: For 12G-SDI designs, Intel recommends to place the refclk pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design.
  • Parallel loopback with external VCXO
    • Use a minimum clock frequency of 148.5 MHz to meet jitter performance specification.
    • If you use a higher clock frequency, you would need to modify the TX PLL reference clock value in the TX PLL parameter editor.
  • Parallel loopback without external VCXO
    • The recommended frequency is 100 MHz (single-rate/triple-rate) or 245 MHz (multi-rate).
  • Serial loopback
    • For this design, the TX PLL refclock is configured to generate clock for integer frame rate.
    • Use a minimum clock frequency of 148.5 MHz to meet jitter performance specification.
    • If you use a higher clock frequency, you would need to modify the TX PLL reference clock value in the TX PLL parameter editor.
TX PLL Alt Refclock tx_pll_refclk_alt Second TX PLL reference clock which can be any clock frequency that is divisible by transceiver for that data rate. This clock must be connected to a dedicated transceiver reference clock pin.
Note: For 12G-SDI designs, Intel recommends to place the refclk pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design.
  • Serial loopback
    • For this design example, TX PLL alt refclock is configured to generate clock for fractional frame rate.
    • Use a minimum clock frequency of 148.35 MHz to meet jitter performance specification.
    • If you use a higher clock frequency, you would need to modify the TX PLL reference clock value in the TX PLL parameter editor.
TX Transceiver Clockout tx_vid_clkout Recovered clock from the transceiver.
  • HD-SDI single rate
    • 74.25 MHz (default)
    • 74.1758 MHz (for the Dynamic TX clock switching feature when you transmit video format with fractional frame rate)
  • 3G-SDI single rate, triple rate or multi rate
    • 148.5 MHz (default)
    • 148.35 MHz (for the Dynamic TX clock switching feature when you transmit video format with fractional frame rate)
TX PLL Serial Clock tx_serial_clk

Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.

RX Refclock rx_cdr_refclk

Transceiver clock data recovery (CDR) reference clock, of any frequency divisible by the transceiver for that data rate. Only a single reference clock frequency is required to support both integer and fractional frame rates. It must be a free running clock connected to the transceiver clock pin.

For the Intel® Stratix® 10 design example, a clock frequency of 148.5 MHz is used as a reference clock in all variants.

Using a higher clock frequency would require a modification of the RX CDR reference clock value in the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP core parameter editor. For triple or multi-rate modes, you need to modify the reference clock value for every profile. Refer to the Changing RX CDR in Transceiver Native PHY IP Core section in the SDI II Intel FPGA IP User Guide.

Note: Do not share the TX PLL reference clock with the RX transceiver reference clock for a parallel loopback design. In parallel loopback designs, the TX PLL clock is tuned to match the RX recovered clock frequency.
rx_core_refclk

SDI RX core reference clock.

The required frequency is 148.5/148.35 MHz or 297/296.7 MHz depending on what you specify for the Rx core clock (rx_coreclk) frequency parameter. This clock must be a free-running clock.

Note: For SDI II Intel® FPGA IP versions 19.1 and later, all Intel® Stratix® 10 design examples have the default setting of 148.5/148.35 MHz to align with the transceiver reference clock frequency.
Note: For Intel® Stratix® 10 devices, assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
  • Uses channel 0 and channel 3 in a transceiver bank.
  • SDI RX and TX cores are placed in either one of these channels.
  • Both SDI RX and RX cores are in multi-rate mode.
RX Transceiver Clkout rx_vid_clkout

Recovered clock from the transceiver.

  • SD-SDI
    • 148.5 MHz (default)
  • HD-SDI
    • 74.25 MHz when receiving integer frame rate
    • 74.1758 MHz when receiving fractional frame rate
  • 3G/6G/12-SDI
    • 148.5 MHz when receiving integer frame rate
    • 148.35 MHz when receiving fractional frame rate
Management Clock rx_rcfg_mgmt_clk

A free-running clock used by Avalon-MM interfaces for reconfiguration and by the PHY reset controller for transceiver reset sequence. The design example uses a frequency of 148.5 MHz to share between this clock and rx_coreclk.

This clock also clocks the reset delay block in the device initialization module. Assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
  • Uses channel 0 and channel 3 in a transceiver bank.
  • SDI RX and TX cores are placed in either one of these channels.
  • Both SDI RX and RX cores are in multi-rate mode.
Component Required Frequency (MHz)

Avalon-MM reconfiguration

100 – 150

Transceiver PHY reset controller

 1 – 500
tx_rcfg_mgmt_clk

A free-running clock used by Avalon-MM interfaces for reconfiguration and by the PHY reset controller for transceiver reset sequence. The design example uses a frequency of 148.5 MHz to share between this clock and rx_coreclk.

This clock also clocks the reset delay block in the device initialization module. Assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
  • Uses channel 0 and channel 3 in a transceiver bank.
  • SDI RX and TX cores are placed in either one of these channels.
  • Both SDI RX and RX cores are in multi-rate mode.
Component Required Frequency (MHz)

Avalon-MM reconfiguration

100 – 150

Transceiver PHY reset controller

 1 – 500
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