2.4. Clocking Scheme Signals
Clock | Signal Name in Design | Description | |
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TX PLL Refclock | tx_pll_refclk |
TX PLL reference clock, of any frequency that is divisible by the transceiver for that data rate. You must connect this clock to a dedicated transceiver reference clock pin.
Note: For 12G-SDI designs, Intel recommends to place the refclk pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design.
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TX PLL Alt Refclock | tx_pll_refclk_alt | Second TX PLL reference clock which can be any clock frequency that is divisible by transceiver for that data rate. This clock must be connected to a dedicated transceiver reference clock pin.
Note: For 12G-SDI designs, Intel recommends to place the refclk pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design.
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TX Transceiver Clockout | tx_vid_clkout | Recovered clock from the transceiver.
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TX PLL Serial Clock | tx_serial_clk | Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate. |
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RX Refclock | rx_cdr_refclk | Transceiver clock data recovery (CDR) reference clock, of any frequency divisible by the transceiver for that data rate. Only a single reference clock frequency is required to support both integer and fractional frame rates. It must be a free running clock connected to the transceiver clock pin. For the Intel® Stratix® 10 design example, a clock frequency of 148.5 MHz is used as a reference clock in all variants. Using a higher clock frequency would require a modification of the RX CDR reference clock value in the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP core parameter editor. For triple or multi-rate modes, you need to modify the reference clock value for every profile. Refer to the Changing RX CDR in Transceiver Native PHY IP Core section in the SDI II Intel FPGA IP User Guide.
Note: Do not share the TX PLL reference clock with the RX transceiver reference clock for a parallel loopback design. In parallel loopback designs, the TX PLL clock is tuned to match the RX recovered clock frequency.
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rx_core_refclk | SDI RX core reference clock. The required frequency is 148.5/148.35 MHz or 297/296.7 MHz depending on what you specify for the Rx core clock (rx_coreclk) frequency parameter. This clock must be a free-running clock.
Note: For SDI II Intel® FPGA IP versions 19.1 and later, all Intel® Stratix® 10 design examples have the default setting of 148.5/148.35 MHz to align with the transceiver reference clock frequency.
Note: For Intel® Stratix® 10 devices, assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
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RX Transceiver Clkout | rx_vid_clkout | Recovered clock from the transceiver.
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Management Clock | rx_rcfg_mgmt_clk | A free-running clock used by Avalon-MM interfaces for reconfiguration and by the PHY reset controller for transceiver reset sequence. The design example uses a frequency of 148.5 MHz to share between this clock and rx_coreclk.
This clock also clocks the reset delay block in the device initialization module. Assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
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Component | Required Frequency (MHz) | ||
Avalon-MM reconfiguration |
100 – 150 |
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Transceiver PHY reset controller |
1 – 500 | ||
tx_rcfg_mgmt_clk | A free-running clock used by Avalon-MM interfaces for reconfiguration and by the PHY reset controller for transceiver reset sequence. The design example uses a frequency of 148.5 MHz to share between this clock and rx_coreclk.
This clock also clocks the reset delay block in the device initialization module. Assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
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Component | Required Frequency (MHz) | ||
Avalon-MM reconfiguration |
100 – 150 |
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Transceiver PHY reset controller |
1 – 500 | ||