SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

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ID 683368
Date 12/09/2022
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel® FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

2.8. Simulation Testbench

The simulation testbench checks for the assertion of the trs_locked signal. The testbench also detects the number of transceiver reconfiguration triggered after every video standard switching.
Figure 17. Simplex Mode Simulation Testbench Block Diagram
Figure 18. Duplex Mode Simulation Testbench Block Diagram
Table 22.  Testbench Components
Component Description
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX and video pattern generator blocks.
RX Checker This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number.
TX Checker This checker verifies if the TX serial data contains a valid TRS signal.
Figure 19. Sequence of Video Standards for Triple-Rate and Multi-Rate Designs
For single-rate designs, only one video standard is tested:
  • HD-SDI single-rate—HD
  • 3G-SDI single-rate—3G Level A 10-bit Multiplex
If you enable the Dynamic Tx Clock Switching parameter, only one video standard is being tested with 2 different TX PHY reference clocks to demonstrate the switching:
  • HD-SDI single-rate—HD
  • 3G-SDI single-rate/triple-rate—3G Level A 10-bit Multiplex
  • Multi-rate—12G 10-bit Multiplex Type 1
Figure 20. Simulation Waveform
A successful simulation ends with the following message: 
#### TRANSMIT TEST COMPLETED SUCCESSFULLY! ####
#  
#### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####
Level Two Title