2.3. Design Components

SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

Download PDF

ID 683368

Date 12/09/2022

Version

Public

Visible to Intel only — GUID: rbz1471943763490

Ixiasoft

2.3. Design Components

The SDI II Intel® FPGA IP core design examples require the following components.

Table 11. Device Under Test (DUT) Components
Design Component	Description
SDI II Intel® FPGA IP	TX The TX core receives the video data from the top level and encodes the necessary information, (e.g. line number (LN), cyclical redundancy check (CRC), payload ID), into the data stream(s). In a multi-rate design, the TX core oversamples the received data up to 11.88 Gbps data rate for every video standard. Specify the assignment of the parallel data interface (`tx_parallel_data`) to the transceiver based on the 11.88 Gbps data rate settings. RX The RX core receives the parallel data from the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP core and decodes information. This information includes descrambling, realigning data, and extracting the necessary information for user. For a multi-rate design, due to the difference in data widths recovered for different video standards, rearrange `rx_parallel_data` from the transceiver before passing the data back to the protocol block.
L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP	TX Native PHY IP block that receives parallel data from the SDI II Intel® FPGA IP core and serializes the data before transmission. For HD/3G-SDI single-rate and triple-rate designs, enable the simplified data interface option to connect parallel data directly to the `tx_dataout` signal of the SDI II Intel® FPGA IP core. For a multi-rate design, disable this option due to the limitation in the 12G-SDI transceiver PHY settings. RX Native PHY block that receives serial data from an external video source. For HD/3G-SDI single-rate and triple-rate designs, enable the simplified data interface option to connect parallel data directly to the `rx_datain` signal of SDI II Intel® FPGA IP core. For a multi-rate design, disable this option due to the limitation in the 12G-SDI transceiver PHY settings. Note: You must connect the `rx_analogreset_stat` output signal from this block to the RX Reconfiguration Management module to indicate that the transceiver is in reset. The maximum parallel data width on the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP core can only go up to 40 bits. Therefore, the design requires a PHY adapter block to be compatible with the SDI II Intel® FPGA IP core. For the duplex mode transceiver (SDI triple-rate parallel loopback with external VCXO design example), generate a dummy RX only PHY ( sdi_rx_phy.ip) to get the transceiver configuration files (_CFG0.sv, _CFG1.sv, …) for RX reconfiguration. The generated configuration files from the duplex mode transceiver may contain some TX registers. You need not reconfigure the registers because only the SDI RX core requires transceiver reconfiguration.
Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP	TX The reset input of this controller is triggered from the top level. The controller generates the corresponding analog and digital reset signal to the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP block, according to the reset sequencing inside the block. Use the `tx_ready` output signal from the block as a reset signal to the TX core to indicate that the transceiver is up and running, and ready to receive data from the core. RX The reset input of this controller is triggered by the SDI II Intel® FPGA IP core. The controller generates the corresponding analog and digital reset signal to the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP block according to the reset sequencing inside the block.
RX Reconfiguration Management	RX transceiver reconfiguration management block that reconfigures the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP block to receive different data rates from SD-SDI to 12G-SDI standards. To indicate the status of the transceiver, connect `rx_cal_busy` and `rx_analogreset_stat` from the transceiver to this block. Note: If you want to use the reconfiguration management block in your own design, you need to make some assignments in the QSF file. For guidelines about how to make the QSF assignments, refer to the Using Generated Reconfiguration Management for Triple and Multi Rates section in the SDI II Intel® FPGA IP User Guide.
TX Reconfiguration Management	TX PLL or transceiver reconfiguration management block that reconfigures the TX PLL or L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP block to change the TX clock dynamically for switching between integer and fractional frame rates. The block requires `tx_cal_busy`, `pll_cal_busy`, and `tx_analogreset_stat` from the transceiver, and the PLLs to indicate the status of the transceiver in a TX PLL switching design.
TX PLL/TX PLL Alt	Transmitter PLL block that provides the serial fast clock to Transceiver Native PHY. For TX PLL switching design, TX PLL is always configured to generate integer frame rate while TX PLL Alt is configured to generate fractional frame rate. For TX PLL reference clock switching design, TX PLL is configured to have reference clock 0 to generate integer frame rate and reference clock 1 to generate fractional frame rate. For single-rate and triple-rate designs, this PLL can be CMU PLL, ATX PLL, or fPLL. For multi-rate designs, CMU PLL is not recommended for 12G data rate. Use fPLL or ATX PLL instead. For parallel loopback without external VCXO multi-rate designs. The design example provides an ATX-fPLL cascading configuration for optimal jitter performance. Move the TX PLL out from the TX top if you want to merge the PLL between multiple channels.
Multi-Rate PHY Adapter	An adapter block which includes mixed width DCFIFO for converting the bit width of parallel data between transceiver and SDI II Intel® FPGA IP core. This block is required in the Intel® Stratix® 10 design because its transceiver does not support 80-bit parallel data interface.

Table 12. Loopback Components
Component	Description
Loopback FIFO	This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data transmission across asynchronous clock domains—the receiver recovered clock and transmitter clock out. The receiver sends the decoded RX data to the transmitter through this FIFO buffer. When the receiver locks, the RX data is written to the FIFO buffer. The transmitter starts reading, encoding, and transmitting the data when half of the FIFO buffer is filled.
Phase Frequency Detector (PFD)	You require this soft PFD block when you use the Intel® Stratix® 10 FPGA development kit on-board Si516 VCXO for a parallel loopback design. This block compares the phase between the receiver and transmitter parallel clocks, and generates an up or down signal, that connects to the Si516 VCXO. These up/down signals control the voltage of the VCXO, so that the frequencies of both clock domains can be tuned as close as possible to each other. Note: Applicable only for single-rate and triple-rate parallel loopback with external VCXO designs.
Reclock	The parallel loopback without external VCXO design requires this module. This block compares the phase between the receiver and transmitter parallel clocks. The output interfaces of this block connect to the reconfiguration Avalon Memory-Mapped (Avalon-MM) interfaces of an fPLL or ATX PLL block. If there is any difference in the frequencies between the clock domains, this module generates the necessary signals to reconfigure the fPLL or ATX PLL block to match the clock frequencies as close as possible. Note: Applicable only for parallel loopback without external VCXO designs.

Table 13. Video Pattern Generator Components
Component	Description
Video Pattern Generator	Basic video pattern generator which supports SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. The generator enables you to select static video with colorbar pattern or pathological pattern.
Pattern Gen Control PIO	Provides a memory-mapped interface for controlling the video pattern generator.
JTAG to Avalon Master Bridge	Provides System Console host access to the Parallel I/O (PIO) IP core in the design through the JTAG interface.

Table 14. Common Block
Component	Description
Transceiver Arbiter	This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations. This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel. The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding `tx_reconfig_cal_busy` or `rx_reconfig_cal_busy` is gated accordingly.
Device Initialization (device_init)	This module contains the Intel® Stratix® 10 Reset Release IP to provide a known initialized state for the system logic to begin operation. This module also includes a reset delay block to further delay the signal status from the IP for a safer operation. For more information about the Intel® Stratix® 10 Reset Release IP, refer to the Intel® Stratix® 10 Reset Release IP section in the Intel® Stratix® 10 Configuration User Guide.