Unified FFT Intel® FPGA IPs User Guide

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ID 683366
Date 6/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Unified FFT Intel FPGA IPs 2. Getting Started with the Unified FFT Intel FPGA IP 3. Bit-reverse Intel® FPGA IP 4. FFT Intel FPGA IP 5. Parallel FFT Intel FPGA IP 6. Variable Size Bit-reverse Intel FPGA IP 7. Variable Size FFT Intel FPGA IP 8. Unified FFT Intel FPGA IPs User Guide Archive 9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide
1. About the Unified FFT Intel FPGA IPs x
1.1. Features of the Unified FFT Intel FPGA IPs 1.2. Unified FFT Intel FPGA IPs Device Family Support 1.3. Release Information for the Unified FFT IPs 1.4. Supported Data Types 1.5. FFT Spectrum 1.6. Global Enable
2. Getting Started with the Unified FFT Intel FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating a Unified FFT IP 2.3. Compiling the Software Model for the Unified FFT IPs 2.4. Running the Unified FFT IPs Automatic Testbench
1. About the Unified FFT Intel FPGA IPs
2. Getting Started with the Unified FFT Intel FPGA IP
3. Bit-reverse Intel® FPGA IP
4. FFT Intel FPGA IP
5. Parallel FFT Intel FPGA IP
6. Variable Size Bit-reverse Intel FPGA IP
7. Variable Size FFT Intel FPGA IP
8. Unified FFT Intel FPGA IPs User Guide Archive
9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide

6. Variable Size Bit-reverse Intel FPGA IP

This IP performs radix-2 FFT bit reverse operation. The size of the input stream may be variable. You may use this IP to bit-reverse the input or the output of FFT Intel FPGA IP.
Figure 4. Example use of the Variable Size Bit-reverse Intel FPGA IP

If the input data width is smaller than the output data width, bit-reversing the input reduces memory usage in the Bit-reverse Intel FPGA IP. However, when the input is bit-reversed, the memory usage of the FFT Intel FPGA IP increases. You should experimentally determine the best configuration for memory usage.

Table 12.  Variable Size Bit-reverse Intel FPGA IP Input Signals
Name Description
clk All input signals must be synchronous to this clock.
rst

Reset signals.

The reset signal is asynchronous for Arria® 10 and Cyclone® 10 GX device; synchronous for Agilex™ 5, Agilex™ 7, and Stratix® 10.

If the reset is asynchronous, deassert the reset signal synchronously to the input clock to avoid metastability issues.

Select the reset polarity with the Reset polarity parameter.

validIn

Data valid signal. Assert this signal when input data is valid.

This signal must not deassert during an FFT. Keep it asserted from the first input to last input of an FFT.
channelIn Not used. Connect it to ground.
d

Data input signal.

This signal contains the real and complex data, size of the FFT, and the optional enable. The size of the FFT is represented as a logarithm to base 2. For example, a value of 2 represents a 4-point FFT and 16 represents a 64K-point FFT The signal order is from least significant bit (LSB) to most significant bit (MSB):

  1. Real data input
  2. Imaginary data input (if complex)
  3. Size of the current FFT
  4. Global enable input (if requested)

Do not set the size input (which dynamically controls the current FFT size) to a value larger than the value specified by Log2(Maximum Size).

Table 13.  Variable Size Bit-reverse Intel FPGA IP Output Signals
Name Description
validOut Data valid signal. The IP asserts this signal for valid output data.
channelOut Not used.
q

Data output signal.

This signal contains real and complex data and size of the FFT. The size of the FFT is represented as a logarithm to base 2. For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT. The signals are in the following order from LSB to MSB:

  1. Real output
  2. Imaginary output (if complex)
  3. Size of the current FFT
Table 14.  Variable Size Bit-reverse Intel FPGA IP Parameters
Parameter Value Description
Core Parameters
Complex input - Select if input should be treated as a complex value.
Log2(Maximum Size) 2 to 16

Specify the maximum size of the FFT.

For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT.
Reset polarity

Active High

Active Low

 Select the reset polarity.
Signal Widths
Input width 4 to 64

Specify the width of the real or complex data input in bits.

If the input is complex, the IP applies the input width separately to the real and imaginary components of the complex signal. The total width of the complex signal is double the value of this parameter.

Generation Parameters
Generate a global enable signal - Select to generate a global enable signal, which you can use to enable and disable the IP. This enable doesn't force the output valid signal to go low.
Generate a software model - Select to generate a software model of the IP in C++ language.
Generate a cycle-accurate software model -

Select to generate a cycle-accurate software model. If this option is not selected the generated software model is not cycle accurate with respect to RTL of the IP.

Only available when you select Generate a software model .

Generate HLD external function wrappers -

Select to generate wrapper files so that you can use the IP as an external function with HLD tools such as HLS and OpenCL.

Only available if generating a software model.
Frequency target 20 to 2000

Specify the frequency at which the IP is required to operate in MHz.

The Frequency target affects the RTL generation for that IP.

Device family -

Specifies the device family the IP is targeting.

Usually, the Intel Quartus project sets this value. If using other tools such as qsys-generate, refer to those tools’ documentation.

The Device family affects the RTL generation for that IP.

Speed grade -

Specifies the speed grade of the device the IP is required to operate on.

Usually, the Intel Quartus project sets this value. If using other tools such as qsys-generate, refer to those tools’ documentation.

The Speed grade affects the RTL generation for that IP.

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