Unified FFT Intel® FPGA IPs User Guide

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ID 683366
Date 6/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Unified FFT Intel FPGA IPs 2. Getting Started with the Unified FFT Intel FPGA IP 3. Bit-reverse Intel® FPGA IP 4. FFT Intel FPGA IP 5. Parallel FFT Intel FPGA IP 6. Variable Size Bit-reverse Intel FPGA IP 7. Variable Size FFT Intel FPGA IP 8. Unified FFT Intel FPGA IPs User Guide Archive 9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide
1. About the Unified FFT Intel FPGA IPs x
1.1. Features of the Unified FFT Intel FPGA IPs 1.2. Unified FFT Intel FPGA IPs Device Family Support 1.3. Release Information for the Unified FFT IPs 1.4. Supported Data Types 1.5. FFT Spectrum 1.6. Global Enable
2. Getting Started with the Unified FFT Intel FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating a Unified FFT IP 2.3. Compiling the Software Model for the Unified FFT IPs 2.4. Running the Unified FFT IPs Automatic Testbench
1. About the Unified FFT Intel FPGA IPs
2. Getting Started with the Unified FFT Intel FPGA IP
3. Bit-reverse Intel® FPGA IP
4. FFT Intel FPGA IP
5. Parallel FFT Intel FPGA IP
6. Variable Size Bit-reverse Intel FPGA IP
7. Variable Size FFT Intel FPGA IP
8. Unified FFT Intel FPGA IPs User Guide Archive
9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide

5. Parallel FFT Intel FPGA IP

The IP performs parallel streaming FFT and inverse FFT operations. The IP accepts a user specified number of FFT inputs on parallel wires. This IP uses a hybrid architecture using parallel and serial FFT stages.
Table 9.  Parallel FFT Intel FPGA IP Input Signals
Name Description
clk All input signals must be synchronous to this clock.
rst

Reset signals.

The reset signal is asynchronous for Arria® 10 and Cyclone® 10 GX device; synchronous for Agilex™ 5, Agilex™ 7, and Stratix® 10.

If the reset is asynchronous, deassert the reset signal synchronously to the input clock to avoid metastability issues.

Select the reset polarity with the Reset polarity parameter.

validIn

Data valid signal. Assert this signal when input data is valid.

This signal must not deassert during an FFT. Keep it asserted from the first input to last input of an FFT.

channelIn Not used. Connect it to ground.
d

Data input signal.

This signal contains the optional enable and complex inputs. The signal order is from least significant bit (LSB) to most significant bit (MSB):

  1. First real data input
  2. First imaginary data input
  3. ...
  4. Last real data input
  5. Last imaginary data input
  6. Global enable input (if requested)
Table 10.  Parallel FFT Intel FPGA IP Output Signals
Name Description
validOut Data valid signal. The IP asserts this signal for valid output data.
channelOut Not used.
q

Data output signal.

This signal contains the size and complex or real outputs. The signals are in the following order from LSB to MSB:

  1. First real output
  2. First imaginary output
  3. ...
  4. Last real output
  5. Last imaginary output
Table 11.  Parallel FFT Intel FPGA IP Parameters
Parameter Value Description
Core Parameters
Inverse FFT -

Specify if the operation is an FFT or inverse FFT.

Turn on for an inverse FFT; turn off to compute a normal FFT.
Bit-reversed input

Specify if the input is in natural or bit-reversed order.

Turn on for the IP to receive its input in bit-reversed order and to produce its output in natural order. Turn off for the IP to receive its input in natural order and to produce its output in bit-reversed order.

Log2(Size) 2 to 16

Specify the size of the FFT.

For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT.
Log2(Wires) 1 to 5

Specify the number of parallel inputs. For example, a value of 1 means 2 parallel data inputs and a value of 5 means 32 parallel data inputs.

Number of serial stages 0 to (Log2(Size)-Log2(Wires))

Specify the number of serial stages of the hybrid architecture.

The hybrid architecture consists of zero-or-more serial stages combined with one-or-more parallel stages.

This number controls the architecture that implements the FFT and affects its resource usage and latency.
Datatypes

Fixed Point

Floating Point

 Select a fixed-point or floating-point FFT.
Floating point types

Single

Double

Custom

Select a floating-point format.

Only available when Datatypes is Floating Point.

Reset polarity

Active High

Active Low

 Select the reset polarity.
Signal Widths
Input width 4 to 32

Specify the width of the input in bits.

The input is a complex value. The IP applies the Input width separately to the real and imaginary components of the complex signal. The total width of the complex signal is double the value of this parameter.

Only available when Datatypes is Fixed Point.

Twiddle width 4 to 32

Specify the width of the twiddle constants.

The twiddle constants are complex values. The IP applies the Twiddle width separately to the real and imaginary components of the complex signal. The total width of the complex signal is double the value of this parameter.

Exponent width 5 to 11

Specify the width of the floating point exponent.

Only available when Floating point type is Custom.

Mantissa width 7 to 52

Specify the width of the floating-point mantissa.

Only available when Floating point type is Custom.

Twiddle Parameters
Pruning scheme

Full Wordgrowth

Mild Pruning

Prune To Width

Select the pruning scheme.

Each pruning scheme has a different effect on the datapath:

  • Full wordgrowth allows the datapath to grow by one bit at each adder, and at the first multiplier.
  • Mild pruning allows the datapath to grow by one bit at each adder, and at the first multiplier. It also reduces its width by one bit immediately before each multiplier.
  • Prune to width allows the datapath to grow by one bit at each adder, and at the first multiplier. It also reduces its width to be no more than the specified Pruning width immediately before each multiplier.

Whenever pruning is applied to the datapath only the least significant bit(s) of the datapath are removed.

Only available when Datatypes is Fixed Point.

Pruning width 4 to 32

Specify the pruning width. The IP applies the Pruning width separately to the real and imaginary components of the complex signal.

Only available when Pruning scheme is set to Prune To Width.

Generation Parameters
Generate a global enable signal - Select to generate a global enable signal, which you can use to enable and disable the IP. This enable doesn't force the output valid signal to go low.
Generate a software model - Select to generate a software model of the IP in C++ language.
Generate a cycle-accurate software model -

Select to generate a cycle-accurate software model. If this option is not selected the generated software model is not cycle accurate with respect to RTL of the IP.

Only available when you select Generate a software model .

Generate HLD external function wrappers -

Select to generate wrapper files so that you can use the IP as an external function with HLD tools such as HLS and OpenCL.

Only available if generating a software model.
Frequency target 20 to 2000

Specify the frequency at which the IP is required to operate in MHz.

The Frequency target affects the RTL generation for that IP.

Device family -

Specifies the device family the IP is targeting.

Usually, the Intel Quartus project sets this value. If using other tools such as qsys-generate, refer to those tools’ documentation.

The Device family affects the RTL generation for that IP.

Speed grade -

Specifies the speed grade of the device the IP is required to operate on.

Usually, the Intel Quartus project sets this value. If using other tools such as qsys-generate, refer to those tools’ documentation.

The Speed grade affects the RTL generation for that IP.

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