Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

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ID 683358
Date 1/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Cyclone® 10 GX 2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX 3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX 4. CvP Driver and Registers A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide
1. CvP Initialization in Intel® Cyclone® 10 GX x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Cyclone® 10 GX Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX x
3.1. Generating the Synthesis HDL Files for Intel® Cyclone® 10 GX PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Modifying MSEL/DIP switch on Intel® Cyclone® 10 GX Dev-Kit 3.5.4. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Intel® -defined Vendor Specific Capability Header Register 4.3.2. Intel® -defined Vendor Specific Header Register 4.3.3. Intel® Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
1. CvP Initialization in Intel® Cyclone® 10 GX
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX
4. CvP Driver and Registers
A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

3.5.4. Programming CvP Images

You must program the periphery image (.periph.jic) and then download the core image (.core.rbf) using the PCIe Link. You can use JTAG to load different programming files (i.e. .jic/periph.pof) into your selected configuration device and configure CvP initialization enabled Intel® Cyclone® 10 GX device with AS configuration mode.

After loading the periphery image via the configuration device, the link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities.

Follow these steps to program and test the CvP functionality:
  1. Plug the Intel® Cyclone® 10 GX FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. Intel® recommends that you use the ATX power supply that the development kit includes.
  2. On the host PC, open the Intel® Quartus® Prime Tools menu and select Programmer.
  3. Click Auto Detect to verify that the USB Blaster recognizes the Intel® Cyclone® 10 GX FPGA.
  4. Follow these steps to program the periphery image:
    1. Select Intel® Cyclone® 10 GX device, and then right click None under File column.
    2. Navigate to .periph.jic file and click Open.
    3. Under Program/Configure column, select the respective devices. For example, 10CX220YF780E5G and EPCQL1024.
    4. Click Start to program the periphery image into EPCQL1024 flash.
    Figure 10. Illustrating the specified options to the program periphery image
  5. After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the host PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel® Cyclone® 10 GX Development Kit.
  6. You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
  7. Follow these steps to program the core image:
    1. Copy the .core.rbf file to appropriate Intel® Quartus® Prime bin install directory. Depending on the 32-bit or 64-bit system, the folder is …./quartus/bin32 or …./quartus/bin64.
    2. Open a Command Prompt in Windows, change the directory to the same mentioned above where the file is copied.
    3. Type the following command to program the core image:

      quartus_cvp --vid=<Vendor ID> --did=<Device ID> xxx.core.rbf

      where the value of Vendor ID and Device ID are in hexadecimal and specified in the Hard IP for PCI Express dialog box. For example, quartus_cvp --vid=1172 --did=0000 xxx.core.rbf.

    4. You can print out the kernel message using the dmesg to ensure the CvP is completed successfully.
      Figure 11. Command Prompt Console
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