Intel® Hyperflex™ Architecture High-Performance Design Handbook

Download PDF
ID 683353
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Hyperflex™ FPGA Architecture Introduction 2. Intel® Hyperflex™ Architecture RTL Design Guidelines 3. Compiling Intel® Hyperflex™ Architecture Designs 4. Design Example Walk-Through 5. Retiming Restrictions and Workarounds 6. Optimization Example 7. Intel® Hyperflex™ Architecture Porting Guidelines 8. Appendices 9. Intel® Hyperflex™ Architecture High-Performance Design Handbook Archive 10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History
1. Intel® Hyperflex™ FPGA Architecture Introduction x
1.1. Intel® Hyperflex™ Architecture Design Concepts
2. Intel® Hyperflex™ Architecture RTL Design Guidelines x
2.1. High-Speed Design Methodology 2.2. Hyper-Retiming (Facilitate Register Movement) 2.3. Hyper-Pipelining (Add Pipeline Registers) 2.4. Hyper-Optimization (Optimize RTL)
2.1. High-Speed Design Methodology x
2.1.1. Set a High-Speed Target 2.1.2. Experiment and Iterate 2.1.3. Compile Components Independently 2.1.4. Optimize Sub-Modules 2.1.5. Avoid Broadcast Signals
2.1.1. Set a High-Speed Target x
2.1.1.1. Speed and Timing Closure 2.1.1.2. Speed and Latency
2.2. Hyper-Retiming (Facilitate Register Movement) x
2.2.1. Reset Strategies 2.2.2. Clock Enable Strategies 2.2.3. Preserving Registers During Synthesis 2.2.4. Timing Constraint Considerations 2.2.5. Clock Synchronization Strategies 2.2.6. Metastability Synchronizers 2.2.7. Initial Power-Up Conditions 2.2.8. Retiming through RAMs and DSPs
2.2.1. Reset Strategies x
2.2.1.1. Removing Asynchronous Resets 2.2.1.2. Synchronous Resets on Global Clock Trees 2.2.1.3. Synchronous Resets on I/O Ports 2.2.1.4. Duplicate and Pipeline Synchronous Resets
2.2.2. Clock Enable Strategies x
2.2.2.1. Localized Clock Enable 2.2.2.2. High Fan-Out Clock Enable 2.2.2.3. Clock Enable with Timing Exceptions
2.2.4. Timing Constraint Considerations x
2.2.4.1. Optimize Multicycle Paths 2.2.4.2. Overconstraints
2.2.5. Clock Synchronization Strategies x
2.2.5.1. Clock Domain Crossing Constraint Guidelines
2.2.7. Initial Power-Up Conditions x
2.2.7.1. Specifying Initial Memory Conditions 2.2.7.2. Initial Conditions and Retiming 2.2.7.3. Initial Conditions and Hyper-Registers 2.2.7.4. Retiming Reset Sequences
2.2.7.3. Initial Conditions and Hyper-Registers x
2.2.7.3.1. Implementing Clock Gating 2.2.7.3.2. Intel® Quartus® Prime Settings for Initial Conditions
2.3. Hyper-Pipelining (Add Pipeline Registers) x
2.3.1. Conventional Versus Hyper-Pipelining 2.3.2. Pipelining and Latency 2.3.3. Use Registers Instead of Multicycle Exceptions
2.3.2. Pipelining and Latency x
2.3.2.1. Pipelining at Variable Latency Locations 2.3.2.2. Automatic Pipeline Insertion
2.3.2.1. Pipelining at Variable Latency Locations x
2.3.2.1.1. Specifying a Latency-Insensitive False Path
2.3.2.2. Automatic Pipeline Insertion x
2.3.2.2.1. Step 1: Create the Variable Latency Module 2.3.2.2.2. Step 2: Instantiate the Variable Latency Module 2.3.2.2.3. Step 3: Verify Automatic Pipeline Insertion Option 2.3.2.2.4. (Optional) Auto-Pipeline Insertion without a Variable Latency Module
2.4. Hyper-Optimization (Optimize RTL) x
2.4.1. General Optimization Techniques 2.4.2. Optimizing Specific Design Structures
2.4.1. General Optimization Techniques x
2.4.1.1. Shannon’s Decomposition 2.4.1.2. Time Domain Multiplexing 2.4.1.3. Loop Unrolling 2.4.1.4. Loop Pipelining 2.4.1.5. Precomputation
2.4.1.1. Shannon’s Decomposition x
2.4.1.1.1. Shannon’s Decomposition Example 2.4.1.1.2. Identifying Circuits for Shannon’s Decomposition
2.4.1.4. Loop Pipelining x
2.4.1.4.1. Loop Pipelining Theory 2.4.1.4.2. Loop Pipelining Demonstration 2.4.1.4.3. Loop Pipelining and Synthesis Optimization
2.4.2. Optimizing Specific Design Structures x
2.4.2.1. High-Speed Clock Domains 2.4.2.2. Restructuring Loops 2.4.2.3. Control Signal Backpressure 2.4.2.4. Flow Control with FIFO Status Signals 2.4.2.5. Flow Control with Skid Buffers 2.4.2.6. Read-Modify-Write Memory 2.4.2.7. Counters and Accumulators 2.4.2.8. State Machines 2.4.2.9. Memory 2.4.2.10. DSP Blocks 2.4.2.11. General Logic 2.4.2.12. Modulus and Division 2.4.2.13. Resets 2.4.2.14. Hardware Re-use 2.4.2.15. Algorithmic Requirements 2.4.2.16. FIFOs 2.4.2.17. Ternary Adders
2.4.2.1. High-Speed Clock Domains x
2.4.2.1.1. Visualizing Clock Networks 2.4.2.1.2. Viewing Clock Networks in the Fitter Report 2.4.2.1.3. Viewing Clocks in the Timing Analyzer
2.4.2.9. Memory x
2.4.2.9.1. Intel® Hyperflex™ Architecture True Dual-Port Memory 2.4.2.9.2. Use Simple Dual-Port Memories 2.4.2.9.3. Intel® Hyperflex™ Architecture Simple Dual-Port Memory Example 2.4.2.9.4. Memory Mixed Port Width Ratio Limits 2.4.2.9.5. Unregistered RAM Outputs
3. Compiling Intel® Hyperflex™ Architecture Designs x
3.1. Compiling Submodules Independently 3.2. Design Assistant Design Rule Checking
3.2. Design Assistant Design Rule Checking x
3.2.1. Running Design Assistant During Compilation 3.2.2. Running Design Assistant in Analysis Mode
3.2.2. Running Design Assistant in Analysis Mode x
3.2.2.1. Cross-Probing from Design Assistant to Visualization Tools 3.2.2.2. Launching Design Assistant from Chip Planner 3.2.2.3. Launching Design Assistant from Timing Analyzer
4. Design Example Walk-Through x
4.1. Median Filter Design Example
4.1. Median Filter Design Example x
4.1.1. Step 1: Compile the Base Design 4.1.2. Step 2: Add Pipeline Stages and Remove Asynchronous Resets 4.1.3. Step 3: Add More Pipeline Stages and Remove All Asynchronous Resets 4.1.4. Step 4: Optimize Short Path and Long Path Conditions
5. Retiming Restrictions and Workarounds x
5.1. Setting the dont_merge Synthesis Attribute 5.2. Interpreting Critical Chain Reports
5.2. Interpreting Critical Chain Reports x
5.2.1. Insufficient Registers 5.2.2. Short Path/Long Path 5.2.3. Fast Forward Limit 5.2.4. Loops 5.2.5. One Critical Chain per Clock Domain 5.2.6. Critical Chains in Related Clock Groups 5.2.7. Complex Critical Chains 5.2.8. Extend to locatable node 5.2.9. Domain Boundary Entry and Domain Boundary Exit 5.2.10. Critical Chains with Dual Clock Memories 5.2.11. Critical Chain Bits and Buses 5.2.12. Delay Lines
5.2.1. Insufficient Registers x
5.2.1.1. Insufficient Registers Example 5.2.1.2. Optimizing Insufficient Registers 5.2.1.3. Critical Chains with Dual Clock Memories
5.2.2. Short Path/Long Path x
5.2.2.1. Hyper-Register Locations Not Available 5.2.2.2. Example for Hold Optimization 5.2.2.3. Optimizing Short Path/Long Path 5.2.2.4. Add Registers 5.2.2.5. Duplicate Common Nodes 5.2.2.6. Data and Control Plane
5.2.3. Fast Forward Limit x
5.2.3.1. Optimizing Path Limit
5.2.4. Loops x
5.2.4.1. Example of Loops Limiting the Critical Chain
6. Optimization Example x
6.1. Round Robin Scheduler
7. Intel® Hyperflex™ Architecture Porting Guidelines x
7.1. Design Migration and Performance Exploration 7.2. Top-Level Design Considerations
7.1. Design Migration and Performance Exploration x
7.1.1. Black-boxing Verilog HDL Modules 7.1.2. Black-boxing VHDL Modules 7.1.3. Clock Management 7.1.4. Pin Assignments 7.1.5. Transceiver Control Logic 7.1.6. Upgrade Outdated IP Cores
8. Appendices x
8.1. Appendix A: Parameterizable Pipeline Modules 8.2. Appendix B: Clock Enables and Resets
8.2. Appendix B: Clock Enables and Resets x
8.2.1. Synchronous Resets and Limitations 8.2.2. Retiming with Clock Enables 8.2.3. Resolving Short Paths
8.2.1. Synchronous Resets and Limitations x
8.2.1.1. Synchronous Resets Summary
8.2.2. Retiming with Clock Enables x
8.2.2.1. Example for Broadcast Control Signals
1. Intel® Hyperflex™ FPGA Architecture Introduction
2. Intel® Hyperflex™ Architecture RTL Design Guidelines
3. Compiling Intel® Hyperflex™ Architecture Designs
4. Design Example Walk-Through
5. Retiming Restrictions and Workarounds
6. Optimization Example
7. Intel® Hyperflex™ Architecture Porting Guidelines
8. Appendices
9. Intel® Hyperflex™ Architecture High-Performance Design Handbook Archive
10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History

10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History

Document Version Intel® Quartus® Prime Version Changes
2021.10.11 21.3
  • Removed obsolete Hyper-Retimer Readiness Rules topic. These rules are now in other rule categories.
  • Replaced missing figure in Step 2: Instantiate the Variable Latency Module topic.
2021.10.04 21.3
  • Revised Step 2: Instantiate the Variable Latency Module with explanation on partition boundary limits, correct use of constraints, and illustrations.
2021.06.21 20.1
  • Added links to Intel® Agilex™ Device Datasheet and Intel® Stratix® 10 Device Datasheet.
2020.07.13 20.1
  • Changed reference from asynchronous reset to synchronous reset in reference to "Retiming Example – Second Register Pushes out of ALM" figure.
  • Updated "Initial Power-Up Conditions" section to reflect latest IP and default state of QSF options.
  • Removed obsolete "Synchronous Start System Clock Gating Examples" topic.
2020.05.01 20.1
  • Added "Clock Domain Crossing Constraint Guidelines" topic.
  • Added Synchronization Register Chain Length assignment details to "Metastability Synchronizers" topic.
2019.12.16 19.4.0
  • Referenced programming file generation support for Intel® Agilex™ devices.
  • Added details, example, and table to "Preserving Registers During Synthesis" topic.
  • Added note and links about reset release requirement to "Reset Strategies" topic.
  • Added "Compiling Submodules Independently" topic.
2019.11.15 19.3.0
  • Added note about assignment precedence to "Specifying a Latency-Insensitive False Path."
  • Clarified insertion of vlat module in "Step 2: Instantiate the Variable Latency Module."
2019.11.04 19.3.0
  • Retitled document from Intel® Stratix® 10 High-Performance Design Handbook and updated throughout to include Intel® Agilex™ devices.
  • Added "Design Rule Checking with Design Assistant" topic.
  • Added "Running Design Assistant During Compilation" topic.
  • Added "Running Design Assistant in Analysis Mode" topic.
  • Added "Cross-Probing from Design Assistant" topic.
  • Added "Running Design Assistant from Chip Planner" topic.
  • Added "Running Design Assistant from Timing Analyzer" topic.
  • Added "Hyper-Retimer Readiness Rules" topic and link to specific rule descriptions.
2019.07.01 19.2.0
  • Improved quality of various screenshots.
  • Updated "Step 1; Compile the Base Design" with results.
  • Added more detail about the purpose of adding the 5 pipeline stages to "Step 2: Add Pipeline Stages and Remove Asynchronous Resets."
  • Minor wording changes and updated figure and table references throughout.
  • Updated link to design example files.
  • Updated diagrams in "Synchronous Resets and Limitations" topic.
2018.12.30 18.1.0
  • Added description of variable latency auto pipelining feature.
  • Updated new section on "Initial Conditions and Hyper-Registers."
  • Added new "Synchronous Start System Example" topic.
  • Added new "Implementing Clock Gating" topic.
2018.10.04 18.0.0
  • Minor text change in "Fast Forward Limit."
  • Minor text change in "Delay Lines."
2018.10.01 18.0.0
  • Corrected typo in "Retiming through RAMs and DSPs."
2018.07.12 18.0.0
  • Updated all code templates in Appendix A: Parameterizable Pipeline Modules.
  • Added Dual Clock Skid Buffer Example to Flow Control with Skid Buffers topic.
  • Updated various screenshots for improved visibility and accuracy of results.
2018.06.22 18.0.0 Corrected error in Original Loop Structure diagram in Loop Pipelining Demonstration.
2018.05.22 18.0.0
  • Retitled Removing Asynchronous Clears to Removing Asynchronous Resets.
  • Converted code images to code examples and corrected code syntax in Removing Asynchronous Resets.
  • Updated signal names in Removing Asynchronous Resets images to match code examples.
  • Corrected syntax error in Shannon's Decomposition Example.
  • Moved information about flow control with skid buffers into new Flow Control with Skid Buffers topic.
  • Enhanced description of FIFO Flow Control Loop with Two Skid Buffers diagram.
  • Clarified description of Improved FIFO Flow Control Loop with Almost Full instead of Full FIFO diagram.
2018.05.07 18.0.0
  • Removed references to dont_touch synthesis attribute.
  • Added Retiming through RAMs and DSPs topic and diagrams.
  • Clarified use of preserve_syn_only synthesis attribute
  • Updated Intel® Quartus® Prime Pro Edition screenshots.
  • Corrected syntax errors in Round Robin Scheduler examples.
  • Updated description of Retime stage to include traditional register retiming.
2018.02.05 17.1.1 Updated link to Median Filter design examples files.

Date

Version

Changes

2017.11.06 17.1.0
  • Revised Design Example Walkthrough steps and results.
  • Provided link to available design example files for each stage.
  • Moved step-by-step design compilation instructions to Design Compilation chapter, Intel® Quartus® Prime Pro Edition Handbook.
  • Added Ternary Adders topic and examples.
  • Added Loop Pipelining topic and examples.
  • Added description of Reset Sequence Requirement report.
  • Updated for latest Intel® branding conventions.
2017.05.08 Quartus® Prime Pro v17.1 Stratix® 10 ES Editions
  • Updated software support version to Quartus® Prime Pro v17.1 Stratix® 10 ES Editions.
  • Added Initial Power-Up Conditions topic.
  • Added Retiming Reset Sequences topic.
  • Added guidelines for high-speed clock domains.
  • Added Fitter Overconstraints topic.
  • Described Hold Fix-up in Fitter Finalize stage.
  • Added statement about Fast Forward compilation support for retiming across RAM and DSP blocks.
  • Added details on coherent RAM to read-modify-write memory description.
  • Added description of Fast Forward Viewer and Hyper-Optimization Advisor.
  • Added Advanced HyperFlex Settings topic.
  • Added Prevent Register Retiming topic.
  • Added Preserve Registers During Synthesis topic.
  • Added Fitter Commands topic.
  • Added Finalize Stage Reports topic.
  • Replaced command line instructions with new GUI steps in compilation flows.
  • Described concurrent analysis controls in Compilation Dashboard.
  • Consolidated duplicate content and grouped Appendices together.
  • Updated diagrams and screenshots.
2016.08.07 2016.08.07
  • Added clock crossing and initial condition timing restriction details.
  • Described true dual-port memory support and memory width ratio with examples
  • Updated code samples and narrative in Design Example Walk-through
  • Added reference to provided Design Example files
  • Re-branded for Intel®
  • Updated for latest changes to software GUI and capabilities.
2016.03.16 2016.03.16 First public release.
Level Two Title