The CF+ card interface is enabled by the host by asserting the H_ENABLE signal. When the CompactFlash card is inserted in the socket, the two pins (CD_1 [1:0]) go low, indicating to the interface that the card has been inserted properly. In response to this action, an interrupt signal H_INT is generated by the interface, depending on the status of CD_1 pins and the chip enable signal (H_ENABLE).

The H_READY signal is also asserted whenever the required conditions are met. This signal indicates to the processor that the interface is ready to accept the data from the processor. The 16-bit data bus to the CF+ card is connected directly to the host. When the host receives an interrupt signal, it responds to it by generating an acknowledgment signal, H_ACK, for the interface to indicate that it has received the interrupt and is ready to perform further functions. This signal acts as an impetus; all operations of the interface, host, or the processor and CompactFlash card are synchronized to this signal. The interface also checks for H_RESET signal; this signal is generated by the host to indicate that all the initial conditions must be reset. The interface in turn generates the RESET signal to the CompactFlash card indicating to it to reset all its control signals to its default condition. The H_RESET signal can either be hardware or software generated. The software reset is indicated by the MSB of the Configuration Option Register within the CF+ card. The host generates a 4-bit control signal H_CONTROL to indicate the desired function of the CF+ card to the CF+ interface. The interface decodes the H_CONTROL signal and issues various control signals to read and write data, and configuration information. Every card operation is synchronized to the H_ACK signal. At the positive edge of the H_ACK, the supported Altera device checks for the reset signal, and correspondingly issues the HOST_ADDRESS, chip enable (CE_1), output enable (OE), write enable (WE), REG_1, and RESET signals. Each of these signals have a predefined value for all the operations mentioned above. These are standard protocols, as defined by the CompactFlash association.

The H_IOM signal is held low in common memory mode and high in I/O mode. The common memory mode allows writing and reading of both 8-bit and 16-bit data. Also, the Configuration Registers in the CF+ card configuration option register, Card Status Register, and Pin Replacement Register are read from and written into. A 4-bit wide H_CONTROL [3:0] signal issued by the host differentiates between all these operations. The CF+ interface decodes H_CONTROL and issues the control signals to the CF+ card according to the CF+ specifications. Data is made available on the 16-bit data bus after the control signals are issued. In the I/O mode, the software reset (generated by making the MSB of the Configuration Option Register in the CF+ card high) is checked. Byte and word access operations are executed by the interface in a manner similar to those in the memory mode detailed above.