AN 492: CF+ Interface Using Altera MAX Series

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ID 683351
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. CF+ Interface Using Altera MAX Series
1. CF+ Interface Using Altera MAX Series x
1.1. Using the CF+ Interface with Altera Devices 1.2. Implementation 1.3. Acknowledgments 1.4. Document Revision History
1.1. Using the CF+ Interface with Altera Devices x
1.1.1. Signals
1.2. Implementation x
1.2.1. Source Code
1. CF+ Interface Using Altera MAX Series

1.1.1. Signals

Table 1.  CF+ Interface SignalsThis table lists the CF+ card interfacing signals.
Signal Direction Description
HOST_ADDRESS [10:0] Output These address lines select the following: the I/O port address registers, the memory mapped port address registers, its configuration control and status registers.
CE_1 [1:0] Output This is a 2-bit active-low card select signal.
IORD Output This is an I/O read strobe generated by the host interface to gate the I/O data on the bus from the CF+ card.
IOWR Output This is an I/O write pulse strobe used to clock the I/O data on the card data bus on the CF+ card.
OE Output Active-low output enable strobe.
READY Input In memory mode, this signal is kept high when the CF+ card is ready to accept a new data transfer operation and low when the card is busy.
IREQ Input In the I/O mode operation, this signal is used as an interrupt request. It is strobed low.
REG_1 Output This signal is used to distinguish between common memory and attribute memory accesses. High for common memory and low for attribute memory. In I/O mode, this signal should be active-low when the I/O address is on the bus.
WE Output Active-low signal for writing into the card configuration registers.
RESET Output This signal resets or initializes all registers in the CF+ card.
CD_1 [1:0] Input This is a 2-bit active-low card detect signal.
Table 2.  Host Interface SignalsThis table lists the signals that form the host interface.
Signal Direction Description
H_INT Output Active-low interrupt signal from interface to host indicating insertion of card.
H_READY Output Ready signal from interface to host indicating CF+ is ready to accept new data.
H_ENABLE Input Chip enable
H_ACK Input Acknowledgment to the interrupt request made by the interface.
H_CONTROL [3:0] Input A 4-bit signal selecting between I/O and memory READ/WRITE operations.
H_RESET [1:0] Input A 2-bit signal for hardware and software reset.
H_IOM Input Differentiates memory mode and I/O mode.
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