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Ixiasoft
Visible to Intel only — GUID: nik1411004488319
Ixiasoft
3.4. Transceiver Reference Clock Frequency
The Transceiver reference clock frequency parameter specifies the expected frequency of the pll_ref_clk input clock.
If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.
Per-Lane Data Rate |
Valid pll_ref_clk Frequencies (MHz) |
---|---|
10.3125 |
206.25, 257.8125, 322.265625, 412.5, 515.625, 644.53125 |
12.5, 6.25 |
156.25, 195.3125, 250, 312.5, 390.625, 500, 625 |
The default value of the Transceiver reference clock frequency parameter is 412.5 MHz.