Visible to Intel only — GUID: nik1411004501250
Ixiasoft
Visible to Intel only — GUID: nik1411004501250
Ixiasoft
4.3.1. 100G Interlaken IP Core Clock Signals
Clock Name |
Description |
---|---|
pll_ref_clk | Reference clock for the RX CDR PLL in IP core variations that target an Intel® Arria® 10 device. Reference clock for the RX CDR PLL and the TX transceiver PLL in all other variations. |
tx_serial_clk[NUM_LANES–1:0] | Clocks for the individual transceiver channels in 100G Interlaken IP core variations that target an Intel® Arria® 10 device. |
rx_usr_clk | Clock for the receive application interface. |
tx_usr_clk | Clock for the transmit application interface. |
mm_clk | Management clock for 100G Interlaken IP core register access. |
reconfig_clk | Management clock for Intel® Arria® 10 hard PCS register access, including access for Intel® Arria® 10 transceiver reconfiguration and testing features. |
If you choose to instantiate the optional out-of-band flow control blocks, your 100G Interlaken IP core has additional clock domains.