100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 10/31/2022
Public
Document Table of Contents

7.1. Internal Serial Loopback Mode

The 100G Interlaken IP core supports an internal TX to RX serial loopback mode.

To turn on internal serial loopback:

  • Reset the IP core by asserting and then deasserting the active low reset_n signal.
  • After reset completes, set the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all ones.
    Note: Refer to "IP Core Reset" for information about the required wait period for register access.
  • Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.

Resetting the IP core turns off internal serial loopback. To turn off internal serial loopback:

  • Reset the IP core by asserting and then deasserting the active low reset_n signal. Resetting the IP core sets the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all zeroes.
  • Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in normal operational mode.