Visible to Intel only — GUID: nik1411004534043
Ixiasoft
Visible to Intel only — GUID: nik1411004534043
Ixiasoft
5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
Signal Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
SERDES Pins |
|||
rx_pin |
Input |
Number of lanes |
Each bit represents the differential pair on an RX Interlaken lane. |
tx_pin |
Output |
Number of lanes |
Each bit represents the differential pair on a TX Interlaken lane. |
TX Burst Control Settings |
|||
burst_max_in |
Input |
4 |
Encodes the BurstMax parameter for the IP core. The actual value of the BurstMax parameter must be a multiple of 64 bytes. While traffic is present, this input signal should remain static. However, when no traffic is present, you can modify the value of the burst_max_in signal to modify the BurstMax value of the IP core. The 100G InterlakenIP core supports the following valid values for this signal: 2: 128 bytes 4: 256 bytes 8: 512 bytes |
burst_short_in |
Input |
4 |
Encodes the BurstShort parameter for the IP core. The 100G Interlaken IP core supports the following valid value for this parameter: 2: 64 bytes In general, the presence of the BurstMin parameter makes the BurstShort parameter obsolete. |
burst_min_in |
Input |
4 |
Encodes the BurstMin parameter for the IP core. The IP core supports the following valid values for this signal: 0: Disable optional enhanced scheduling. Intel® recommends you do not drive this value in variations in dual segment mode. If you disable enhanced scheduling, performance is non-optimal. 2: 64 bytes 4: 128 bytes The BurstMin parameter should have a value that is less than or equal to half of the value of the BurstMax parameter. Intel® recommends that you modify the value of this input signal only when no traffic is present on the TX user data interface. You do not need to reset the IP core. |
Real-Time Transmit Status Signals (Synchronous with tx_usr_clk) | |||
tx_lanes_aligned |
Output |
1 |
All of the transmitter lanes are aligned and are ready to send traffic. |
itx_hungry |
Output |
1 |
A dynamic status flag indicating that a downstream buffer which supplies data to the PCS is running empty. The IP core handles this situation by inserting IDLE symbols (IDLE control words) in the packet stream. Therefore, this signal does not indicate an error. This signal is asserted for the duration of the condition it indicates. The PCS runs continuously with the provided data or inserted IDLE symbols. This signal is usually asserted immediately after the IP core comes out of reset. However, the signal can also be asserted during normal operation, and is not a cause for concern. |
itx_overflow |
Output |
1 |
An error flag indicating that the PCS buffer is currently overflowing. This signal is asserted for the duration of the overflow condition: it is asserted in the first clock cycle in which the overflow occurs, and remains asserted until the PCS buffer pointers indicate that no overflow condition exists. |
itx_underflow |
Output |
1 |
An error flag indicating that the PCS buffer is currently underflowed. In normal operation, this signal may be asserted temporarily immediately after the 100G Interlaken IP core comes out of reset. It is asserted as a single cycle wide pulse. |
Real-Time Receiver Status Signals (Synchronous with rx_usr_clk ) |
|||
sync_locked |
Output |
Number of lanes |
Receive lane has locked on the remote transmitter Meta Frame. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line. |
word_locked |
Output |
Number of lanes |
Receive lane has identified the 67-bit word boundaries in the serial stream. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line. |
rx_lanes_aligned |
Output |
1 |
All of the receiver lanes are aligned and are ready to receive traffic. This signal is a level signal. |
crc24_err |
Output |
1 |
A CRC24 error flag covering both control word and data word. This signal does not associate the CRC24 error with a particular packet. Instead, its value indicates the overall SERDES status. You can use this signal to count the number of CRC24 errors. This signal is asserted as a single cycle wide pulse. If the IP core detects back-to-back CRC24 errors, this signal toggles. |
crc32_err |
Output |
Number of lanes |
An error flag indicating diagnostic CRC32 failures per lane. This signal is asserted as a single cycle wide pulse. If back-to-back CRC32 errors are detected, this signal toggles. |
irx_overflow |
Output |
1 |
An error flag indicating the presence of excessive jitter at the receiver side. This signal is included in the current IP core opportunistically for diagnostic purposes. |
rdc_overflow |
Output |
1 |
An error flag indicating that the RX domain-crossing FIFO is currently overflowed. The RX domain-crossing FIFO transfers data from the PCS clock domain to the MAC clock domain. |
rg_overflow |
Output |
1 |
An error flag indicating that the Reassembly FIFO is currently overflowed. The Reassembly FIFO is the receiver FIFO that feeds directly to the user data interface. |
rxfifo_fill_level |
Output |
RXFIFO_ADDR_WIDTH |
The fill level of the Reassembly FIFO, in units of 64-bit words. The width of this signal is the value of the RXFIFO_ADDR_WIDTH parameter, which is 12 by default. You can use this signal to monitor when the RX Reassembly FIFO is empty. |
sop_cntr_inc |
Output |
1 |
A pulse indicating that the 100G Interlaken IP core receiver user data interface received a start-of-packet. You can use this signal to increment a count of SOPs the application observes on the receive interface. |
eop_cntr_inc |
Output |
1 |
A pulse indicating that the 100G Interlaken IP core receiver user data interface received an end-of-packet. You can use this signal to increment a count of EOPs the application observes on the receive interface. |