Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

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ID 683335
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. Traffic Generator 2.3.1.3. Traffic Checker 2.3.1.4. Demo Control 2.3.1.5. Demo Management 2.3.1.6. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

1.3.2. Design Example Parameters

The Serial Lite III Streaming IP parameter editor includes an Example Design tab for you to specify certain parameters before generating the design example.
Table 2.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings. When you select a design from the Preset library, this field shows the selected design.
Generate Files for

The files to generate for different development phases.

Simulation—when selected, the necessary files for simulating the design example are generated.

Synthesis—when selected, the synthesis files are generated. Use these files to compile the design in the Quartus Prime software for hardware testing.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is grayed out, there is no supported board for the options that you select.

Stratix® V GX Transceiver Signal Integrity Development Kit: This option allows you to test the design example on selected Intel development kit. This selection automatically selects the Target Device to match the device on the Intel development kit. If your board revision has a different device grade, you can change the target device.

Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel device, a custom designed board with Intel device, or a standard Intel development kit not available for selection. You can also select a custom device for the custom development kit.

No Development Kit: This option excludes the hardware aspects for the design example.

Change Target Device Select a different device grade for Intel development kit. For device-specific details, refer to the device datasheet on the Intel FPGA website.
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