Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

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ID 683335
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. Traffic Generator 2.3.1.3. Traffic Checker 2.3.1.4. Demo Control 2.3.1.5. Demo Management 2.3.1.6. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

1.1. Directory Structure

The Intel® Quartus® Prime software generates the design example files in the following folders:

  • <user_defined_design_example_directory>/seriallite_iii_sv/ed_sim
  • <user_defined_design_example_directory>/seriallite_iii_sv/ed_synth
  • <user_defined_design_example_directory>/seriallite_iii_sv/ed_hwtest

The following diagrams show the directories that contain the generated files for the design examples.

Figure 2. Directory Structure for Stratix® V Serial Lite III Streaming Design Example
Table 1.  Directory and File Description for Design Example Folder
Directory/File Description
ed_sim/tb_components The folder that contains the testbench files.

ed_sim/cadence

ed_sim/mentor

ed_sim/aldec

ed_sim/synopsys/vcs or ed_sim/synopsys/vcsmx

The folder that contains the simulation script. It also serves as a working area for the simulator.

ed_sim/seriallite_iii_streaming

The folder that contains the design example simulation source files.
ed_synth/seriallite_iii_streaming_demo.qpf Quartus project file.
ed_synth/seriallite_iii_streaming_demo.qsf Quartus settings file.
ed_synth/seriallite_iii_streaming_demo.sdc Synopsys Design Constraints (SDC) file.
ed_synth/src The folder that contains the design example synthesizable components.
ed_synth/src/seriallite_iii_streaming_demo.v Design example top-level HDL.

ed_synth/src/seriallite_iii_streaming/synth/seriallite_iii_streaming.v

Design example DUT top-level files.

ed_synth/src/demo_control

The folder for each synthesizable component including Qsys generated IPs, such as demo_mgmt and demo_control.
ed_hwtest The folder that contains the design example hardware setup files.
ed_hwtest/Readme.txt Instruction file to download the generated design example on the development kit.
ed_hwtest/build_demo_control.sh A script to generate demo control and PLL IPs with NIOS II processor.
ed_hwtest/master_export.v User interface Verilog design file.
ed_hwtest/master_export_hw.tcl Component description file for master export custom IP.
ed_hwtest/software The folder that contains scripts to download the demo_control program into NIOS II processor and open an interactive terminal to run the design example.
Level Two Title