Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

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ID 683335
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. Traffic Generator 2.3.1.3. Traffic Checker 2.3.1.4. Demo Control 2.3.1.5. Demo Management 2.3.1.6. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

2.3.1.2. Traffic Generator

The traffic generator generates traffic in a deterministic format to verify that data is transmitted correctly across the link. Traffic consists of sets of sample words, one for each lane on the link, that are presented to the source user interface.

Figure 9. Traffic Generator Sample Word FormatThis figure shows the format of the sample words generated for each lane.
Table 4.  Traffic Generator Sample Word Fields

Field

Bits

Description

Word ID

63–59

Contains a static value to distinguish which 64-bit word on the user interface that this sample was presented on. The Word ID value ranges from 0 to (lanes – 1).

Burst Count

58–32

Tracks the number of bursts used to transfer the sample data. This field value starts with one after reset and is incremented each time the start_of_burst signal is asserted on the source user interface.

Word Count

31–0

Tracks the number of valid sample words that have been transferred, across all bursts, to the source user interface.

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