Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

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ID 683335
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. Traffic Generator 2.3.1.3. Traffic Checker 2.3.1.4. Demo Control 2.3.1.5. Demo Management 2.3.1.6. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

3.6. Signals

Figure 26. Top-level Signals for Stratix® V Serial Lite III Streaming Advanced Clocking Mode Design Example
Table 9.  Design Example Interface Signals
Signal Direction Width Description
Clock and Reset Signal
mgmt_clk Input 1
Input clock for:
  • Avalon® memory-mapped PHY management interface for Serial Lite III Streaming IP core
  • Demo management module
  • Demo control module
  • Transceiver reset controller
pll_ref_clk Input 1

This reference clock is used by the Clock Data Recovery (CDR) unit in the transceiver. It serves as a reference for the CDR to recover the clock from the serial line. The frequency of this clock must match the frequency you select in the IP parameter editor. It should also match the frequency of the tx_pll_ref_clk reference clock for the TX PLL at the Source variant.

mgmt_reset_n Input 1

Design example asynchronous master reset. Assert this reset signal to reset the overall design example system.

This is an active low signal.
snk_core_reset_n Output 1

Demo management module asserts this signal to reset traffic checker module.

src_core_reset_n Output 1

Demo management module asserts this signal to reset traffic generator module.

Data Signal
rx[n] Input Based on Number of Lanes value

This vector carries the transmitted streaming data from the core.

N represents the number of lanes.

tx[n] Output Based on Number of Lanes value

This vector carries the transmitted streaming data to the core.

N represents the number of lanes.

Status Signal
rx_activity_n Output 1

This single bit signal indicates that the data is valid.
tx_activity_n Output 1

This single bit signal indicates that the data is valid.
snk_link_up_n Output 1

The core asserts this signal to indicate that the core initialization is complete and is ready to receive user data.

src_link_up_n Output 1

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

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