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1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Intel® FPGA IP Evaluation Mode
3.3. Specifying IP Core Parameters and Options
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters
3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs
3.6. IP Generation Output ( Intel® Quartus® Prime Pro Edition)
3.7. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
3.8. Simulating
5.1. IP Architecture
5.2. Transmission Overheads and Lane Rate Calculations
5.3. Reset
5.4. Link-Up Sequence
5.5. Error Detection, Reporting, and Recovering Mechanism
5.6. CRC-32 Error Injection
5.7. FIFO ECC Protection
5.8. User Data Interface Waveforms
5.9. Signals
5.10. Accessing Configuration and Status Registers
5.1.1. Serial Lite III Streaming Source Core
5.1.2. Serial Lite III Streaming Sink Core
5.1.3. Serial Lite III Streaming IP Core Duplex Core
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
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5.1.2. Serial Lite III Streaming Sink Core
The sink core consists of five major functional blocks:
- L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY IP RX core for Intel® Arria® 10 and Intel® Cyclone® 10 GX - Interlaken mode
- Interlaken PHY v18.1 IP RX core ( Stratix® V or Arria® V GZ devices)
- Lane alignment module
- Sink adaptation module (standard clocking mode only)
- Sink application module
- Clock generator (in the standard clocking mode for Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ devices)
Section Content
Sink Application Module
Sink Adaptation Module
Lane Alignment Module
Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode
Sink Clock Generator
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