Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Generic Crosspoint Intel® FPGA IP x
22.1. About the Generic Crosspoint IP 22.2. Generic Crosspoint IP Parameters 22.3. Generic Crosspoint IP Interfaces 22.4. Generic Crosspoint IP Registers 22.5. Generic Crosspoint IP Software API
22.1. About the Generic Crosspoint IP x
22.1.1. Generic Crosspoint IP Features 22.1.2. Generic Crosspoint Performance and Resources
23. Genlock Signal Router Intel® FPGA IP x
23.1. About the Genlock Signal Router IP 23.2. Genlock Signal Router IP Parameters 23.3. Genlock Signal Router IP Interfaces 23.4. Genlock Signal Router IP Registers 23.5. Genlock Signal Router IP Software API
23.1. About the Genlock Signal Router IP x
23.1.1. Genlock Signal Router IP Features 23.1.2. Genlock Signal Router IP Performance and Resources
24. Guard Bands Intel® FPGA IP x
24.1. About the Guard Bands IP 24.2. Guard Bands IP Parameters 24.3. Guard Bands IP Interfaces 24.4. Guard Bands IP Registers 24.5. Guard Bands IP Software API
24.1. About the Guard Bands IP x
24.1.1. Guard Bands IP Performance and Resources
25. Interlacer Intel® FPGA IP x
25.1. About the Interlacer IP 25.2. Interlacer IP Parameters 25.3. Interlacer IP Functional Description 25.4. Interlacer IP Registers 25.5. Interlacer IP Software API
25.1. About the Interlacer IP x
25.1.1. Interlacer IP Performance and Resources
25.3. Interlacer IP Functional Description x
25.3.1. Interlacer IP Interfaces
26. Mixer Intel® FPGA IP x
26.1. About the Mixer IP 26.2. Mixer IP Parameters 26.3. Mixer IP Functional Description 26.4. Mixer IP Registers 26.5. Mixer IP Software API
26.1. About the Mixer IP x
26.1.1. Mixer IP Performance and Resources
26.3. Mixer IP Functional Description x
26.3.1. Mixer IP Interfaces
27. Pixels in Parallel Converter Intel® FPGA IP x
27.1. About the Pixels in Parallel Converter IP 27.2. Pixels in Parallel IP Converter Parameters 27.3. Pixels in Parallel Converter Interfaces 27.4. Pixels in Parallel Converter Registers 27.5. Pixels in Parallel Converter IP Software API
27.1. About the Pixels in Parallel Converter IP x
27.1.1. Pixels in Parallel IP Converter Performance and Resources
28. Scaler Intel® FPGA IP x
28.1. About the Scaler 28.2. Scaler IP Parameters 28.3. Scaler IP Functional Description 28.4. Scaler IP Registers 28.5. Scaler IP Software API
28.1. About the Scaler x
28.1.1. Scaler IP Performance and Resources
28.2. Scaler IP Parameters x
28.2.1. Scaler Maximum Resolution
28.3. Scaler IP Functional Description x
28.3.1. Coefficient Selection 28.3.2. Coefficient Quantization 28.3.3. Partial Frame Scaling 28.3.4. 422 and 420 Chroma Sampled Data Scaling 28.3.5. Scaler IP Interfaces
28.3.1. Coefficient Selection x
28.3.1.1. Updating Scaler IP Runtime Coefficients
29. Stream Cleaner Intel® FPGA IP x
29.1. About the Stream Cleaner IP 29.2. Stream Cleaner IP Parameters 29.3. Stream Cleaner IP Functional Description
29.1. About the Stream Cleaner IP x
29.1.1. Stream Cleaner IP Performance and Resources
29.3. Stream Cleaner IP Functional Description x
29.3.1. Stream Cleaner IP Interfaces
30. Switch Intel® FPGA IP x
30.1. About the Switch IP 30.2. Switch IP Parameters 30.3. Switch IP Functional Description 30.4. Switch IP Registers 30.5. Switch IP Software API
30.1. About the Switch IP x
30.1.1. Switch IP Performance and Resources
30.3. Switch IP Functional Description x
30.3.1. Switch IP Latency 30.3.2. Switch IP Interfaces
31. Tone Mapping Operator Intel® FPGA IP x
31.1. About the Tone Mapping Operator IP 31.2. TMO IP Parameters 31.3. TMO IP Block Description 31.4. TMO IP Registers 31.5. TMO IP Software API
31.1. About the Tone Mapping Operator IP x
31.1.1. TMO IP Features 31.1.2. TMO IP Performance and Resource Utilization
31.3. TMO IP Block Description x
31.3.1. TMO IP Interfaces 31.3.2. TMO IP Latency
32. Test Pattern Generator Intel® FPGA IP x
32.1. About the Test Pattern Generator IP 32.2. Test Pattern Generator IP Parameters 32.3. Test Pattern Generator IP Functional Description 32.4. Test Pattern Generator IP Registers 32.5. Test Pattern Generator IP Software API
32.1. About the Test Pattern Generator IP x
32.1.1. Test Pattern Generator IP Performance and Resources
32.3. Test Pattern Generator IP Functional Description x
32.3.1. Test Pattern Generator IP Interfaces
33. Video Frame Buffer Intel® FPGA IP x
33.1. About the Video Frame Buffer IP 33.2. Video Frame Buffer IP Parameters 33.3. Video Frame Buffer IP Functional Description 33.4. Video Frame Buffer IP Registers 33.5. Video Frame Buffer IP Software API
33.1. About the Video Frame Buffer IP x
33.1.1. Video Frame Buffer Performance and Resources
33.3. Video Frame Buffer IP Functional Description x
33.3.1. Video Frame Buffer IP Interfaces
34. Video Streaming FIFO Intel® FPGA IP x
34.1. About the Video Streaming FIFO IP 34.2. Video Streaming FIFO IP Parameters 34.3. Video Streaming FIFO IP Interfaces
34.1. About the Video Streaming FIFO IP x
34.1.1. Video Streaming FIFO IP Performance and Resources
35. Video Timing Generator Intel® FPGA IP x
35.1. About the Video Timing Generator IP 35.2. Video Timing Generator IP Parameters 35.3. Video Timing Generator IP Functional Description 35.4. Video Timing Generator IP Interfaces 35.5. Video Timing Generator IP Registers 35.6. Video Timing Generator IP Software API
35.1. About the Video Timing Generator IP x
35.1.1. Video Timing Generator IP Features 35.1.2. Video Timing Generator IP Performance and Resources
36. Warp Intel® FPGA IP x
36.1. About the Warp IP 36.2. Warp IP Parameters 36.3. Warp IP Block Description 36.4. Warp IP Registers 36.5. Warp IP Software API
36.1. About the Warp IP x
36.1.1. Warp IP Features 36.1.2. Warp IP Performance and Resource Utilization
36.3. Warp IP Block Description x
36.3.1. Block Cache Tool 36.3.2. Warp IP Interfaces 36.3.3. Warp IP Latency 36.3.4. External Memory for Warp IP
36.5. Warp IP Software API x
36.5.1. Using Warp IP Software 36.5.2. Warp IP Software Code Examples
37. Design Security x
37.1. Memory Subsystems 37.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Generic Crosspoint Intel® FPGA IP
23. Genlock Signal Router Intel® FPGA IP
24. Guard Bands Intel® FPGA IP
25. Interlacer Intel® FPGA IP
26. Mixer Intel® FPGA IP
27. Pixels in Parallel Converter Intel® FPGA IP
28. Scaler Intel® FPGA IP
29. Stream Cleaner Intel® FPGA IP
30. Switch Intel® FPGA IP
31. Tone Mapping Operator Intel® FPGA IP
32. Test Pattern Generator Intel® FPGA IP
33. Video Frame Buffer Intel® FPGA IP
34. Video Streaming FIFO Intel® FPGA IP
35. Video Timing Generator Intel® FPGA IP
36. Warp Intel® FPGA IP
37. Design Security
38. Document Revision History for Video and Vision Processing Suite User Guide

36.4. Warp IP Registers

As the software API allows you to program and control the warp IP, it only has a limited set of registers.
Table 673.  Warp IP RegistersThese registers are all read-only and allow interrogation of the Warp IP’s parameter settings. All the registers are 32-bit wide.
Register Name Offset Address Access Type Description
vid_pid 0x000 RO Warp IP product and vendor ID
version_number 0x004 RO The version for this release of the Warp IP
Reserved 0x008 -
Reserved 0x00C -
pip 0x010 RO Indicates the value of pixels in parallel parameter
color_planes 0x014 RO Indicates the value of number of color planes parameter
cps 0x018 RO Indicates the value of bits per color sample parameter
num_engines 0x01C RO Indicates the value of number of engines parameter
max_input_width 0x020 RO Indicates the value of maximum input video width parameter
max_output_width 0x024 RO Indicates the value of maximum output video width parameter
memory_buffer_size 0x028 RO Indicates the value of memory frame buffer size parameter
easy_warp 0x02C RO Indicates the value of Use easy warp parameter
single_memory_bounce 0x030 RO Indicates the value of Use single memory bounce parameter
cache_blocks 0x034 RO Indicates the value of Cache blocks per engine parameter
Reserved 0x030-0x16C RO -
int_control 0x170 RW Turns on the interrupt
int_status 0x174 RW1C Read interrupt status and clear interrupt
Table 674.   vid_pid Register
Bits Name Description
31:16 VID Vendor ID that returns a value of 0x6AF7
15:0 PID Warp product ID that returns a value of 0x016F
Table 675.   version_number Register
Bits Name Description
31:0 Version Number The version number of the Warp IP
Table 676.   pip Register
Bits Name Description
31:0 Pixels in Parallel The pixel in parallel parameter. Returns a value of 1 or 2.
Table 677.   color_planes Register
Bits Name Description
31:0 Number of Color Planes The number of color planes parameter. Returns a value of 3.
Table 678.   bps Register
Bits Name Description
31:0 Bits per Color Sample The bits per color sample parameter. Returns a value of 10.
Table 679.   num_engines Register
Bits Name Description
31:0 Number of Engines The number of engines parameter. Returns a value of 1 or 2.
Table 680.   max_input_width Register
Bits Name Description
31:0 Maximum input video width The maximum input video width parameter. Returns a value of 2048 or 3840.
Table 681.   max_output_width Register
Bits Name Description
31:0 Maximum output video width The maximum output video width parameter. Returns a value of 2048 or 3840.
Table 682.   memory_buffer_size Register
Bits Name Description
31:0 Memory frame buffer size

The memory frame buffer size parameter. Returns a value of 0, 1 or 2.

0 = SD, 1=HD and 2=UHD
Table 683.   easy_warp Register
Bits Name Description
31:0 Use easy warp The Use easy warp parameter. Returns a value of 0 or 1.
Table 684.   single memory bounce Register
Bits Name Description
31:0 Single memory Bounce The Use single memory bounce parameter. Returns a value of 0 or 1.
Table 685.   cache blocks per engine Register
Bits Name Description
31:0 Cache blocks The Cache blocks per engine parameter. Returns a value of 256, 512 or 1024.
Table 686.   int_control Register
Bits Name Description
0 Interrupt Enable Setting this bit to 1 enables the interrupt. Setting to 0 disables the interrupt.
Table 687.   int_status Register
Bits Name Description
0 Interrupt Status

Reading from this bit returns the status of the interrupt.

Writing a 1 to this bit clears the interrupt. Once triggered, the interrupt remains set until it is cleared by writing a 1 to this bit.

Debug and Measurement Registers

When you turn on Enable Debug Registers in the configuration settings of the Warp IP, a set of read only registers are available that provide various debug and measurement readings. The registers provide information useful during system bring up and debug and are accessed using the software API.

The available measurements are:

  • Input section:
    • INPUT_FRAME_COUNT
    • INPUT_FRAME_PERIOD
  • Output section
    • OUTPUT_FRAME_COUNT
    • OUTPUT_FRAME_PERIOD
  • Engine section
    • ENGINE_FRAME_COUNT
    • ENGINE_FRAME_PERIOD
    • ENGINE_BUSY_CYCLES
    • ENGINE_FRAME_DELAY
    • ENGINE_FAILED_TO_COMPLETE_FRAME
    • ENGINE_RUN_STATUS
    • ENGINE_CACHE_LOADS
  • General section
    • MEM_WR_QUEUES0
    • MEM_WR_QUEUES1
    • MEM_RD_QUEUES0
    • MEM_RD_QUEUES1
Table 688.  Registers
Name Description
Input Section

The IP reads the debug registers relating to the input section of the Warp IP using the intel_vvp_warp_get_input_debug_register () API call.

INPUT_FRAME_COUNT

A count of the number of frames that have started at the input of the Warp IP. The last frame counted may be incomplete.

This counter can indicate the video activity at the input of the Warp IP. Sampling this count periodically indicates frame rate. A static count indicates that the upstream pipeline to the Warp IP is not producing video data.

INPUT_FRAME_PERIOD

The number of axi4s_vid_in_0_clock cycles seen between the last two start of frames seen at the input.

Use this counter to indicate the frame rate by comparing its value with the input clock frequency. If the value from this register varies greatly, it indicates an unstable processing pipeline upstream of the Warp IP.

Output Section

The debug registers relating to the output section of the Warp IP are read using the intel_vvp_warp_get_output_debug_register () API call.

OUTPUT_FRAME_COUNT

A count of the number of frames that have started at the output. The last frame counted may be incomplete.

This counter can indicate the video activity at the output of the Warp IP. Sampling this count periodically gives an indication of frame rate and a static count indicates that the downstream pipeline from the Warp IP is blocked and not accepting video data.

OUTPUT_FRAME_PERIOD

The number of axi4s_vid_out_0_clock cycles seen between the last two start of frames seen at the output.

This counter can indicate the frame rate by comparing its value with the output clock frequency. If the value from this register varies wildly, it indicates an unstable processing pipeline downstream of the Warp IP.

Engine Section

The debug registers relating to the engine section of the Warp IP are read using the intel_vvp_warp_get_engine_debug_register () API call.

ENGINE_FRAME_COUNT

A count of the number of frames that have started to be processed by the engine being referenced. The processing of the last frame counted may be in progress.

This counter is useful for indicating the video activity within the Warp IP. It gives an indication that the Warp IP is set up and that the engine is configured to process correctly.

ENGINE_FRAME_PERIOD

The number of core_clock cycles seen between the last two start of frames seen at the engine.

This counter is useful for confirming that the core_clock is set correctly given the expected frame rate. It is also useful for comparing against the ENGINE_BUSY _CYCLES value as an indication of how busy the engine is.

ENGINE_BUSY CYCLES

The number of core_clock cycles for which the engine actively processes video data during the last frame. The counter starts when the processing of a frame begins and continues until either the IP completes the frame or encounters the start of the next frame. For the latter the engine fails to complete the processing of the frame in time, refer to the ENGINE_FAILED_TO_COMPLETE_FRAME status indicator.

When compared to the ENGINE_FRAME_PERIOD, the value of ENGINE_BUSY_CYCLES gives an indication of how busy an engine is during the processing of a frame.

ENGINE_FRAME_DELAY

The number of core_clock cycles between the start of the last input frame and the start of the engine’s processing phase.

Use this counter for low latency behavior to determine if you have enough delay when programming the low latency settings. It also indicates the input and output frame synchronization that is a requirement for correct low latency behavior. This delay must be stable for low latency IPs to work correctly. If the IP does not see a stable value, the delay is changing over time, which indicates the input to output frame synchronization may not be operating correctly.

ENGINE_FAILED_TO_COMPLETE_FRAME

A sticky flag that indicates that the engine has failed to complete the processing of a frame in the required frame period. The flag is cleared each time it is interrogated.

The IP sets this to indicate that the engine has not had sufficient time to process the video frame as required and image corruption occurs. The most likely reason is insufficient memory bandwidth available to the engine. Insufficient memory bandwidth gives processing stalls either while waiting for read data to return or stalls while blocked waiting for write data is sent out.

ENGINE_RUN_STATUS

This value is only relevant when Use single memory bounce is on.

The lower 16 bits of the value indicate the lowest buffering level the IP reaches during the processing of the previous frame. The buffering level is the difference between the write position and the read position of the current cache accesses. If this value is 0, it indicates that the engine stalls during the processing of the frame. This stall can give unstable output video when Use single memory bounce is on.

The upper 16 bits of the value is the output line at which the IP reaches the lowest buffering level. They indicate at which point in the transform this output line occurs.

ENGINE_CACHE_LOADS The number of cache loads the IP produces while the IP processes the previous frame. Each cache load reads a 16x8 pixel block (128 pixels in total). The total number of cache reads indicates the memory bandwidth load that the current warp transform is placing on the memory.

General Section

The debug registers relating to the general section of the Warp IP are read using the intel_vvp_warp_get debug_register () API call.

MEM_WR_QUEUES0

Indicates the number of internal requests that queue at any one time for each of the write accesses through the Warp IP’s memory controller. The IP stores each queue depth value as a byte in the 32-bit data word returned by the read to this register. The IP has a number of queues depending on the configuration (Separate Queue Values (Write Accesses)).

MEM_RD_QUEUES0 and MEM_RD_QUEUES1

Indicates the number of internal requests that queue at any one time for each of the read accesses through the Warp IP’s memory controller. The IP has two 32 bit registers for access to the read queue depths. Each individual queue depth value is stored as a nibble in the 32 bit data word returned by a read to one of these registers. The IP has a number of queues depending on the configuration (Separate Queue Values (Read Accesses))

Table 689.  Separate Queue Values (Write Accesses)

The table shows the separate queue values for each configuration. The maximum depth value for each write queue is 48. If periodically sampling of the queue depth values finds them to be close to or at this maximum value, it indicates a limitation on write bandwidth from the IP to the external memory because the queues are filling up and blocking throughput.

Queue Use Easy Warp or Use Single Memory Bounce are On Single Engine Dual Engine
Video Input MEM_WR_QUEUES0[7:0] MEM_WR_QUEUES0[7:0] MEM_WR_QUEUES0[7:0]
Engine 0 Write N/A MEM_WR_QUEUES0[15:8] MEM_WR_QUEUES0[15:8]
Engine 1 Write N/A N/A MEM_WR_QUEUES0[23:16]
Table 690.  Separate Queue Values (Read Accesses)The table shows the separate queue values for each configuration.

The maximum value for each read queue depth is 12. If periodically sampling of queue depth values finds them close to or at this maximum value, it indicates a limitation on read bandwidth from the IP to the external memory because the queues are filling up and blocking throughput.

Queue Easy Warp Single Engine Dual Engine
Video Output MEM_RD_QUEUES0[3:0] MEM_RD_QUEUES0[3:0] MEM_RD_QUEUES0[3:0]
Engine 0 Video N/A MEM_RD_QUEUES0[7:4] MEM_RD_QUEUES0[7:4]
Engine 0 Coeff0 N/A MEM_RD_QUEUES0[11:8] MEM_RD_QUEUES0[11:8]
Engine 0 Coeff1 N/A MEM_RD_QUEUES0[15:12] MEM_RD_QUEUES0[15:12]
Engine 0 Coeff2 N/A MEM_RD_QUEUES0[19:16] MEM_RD_QUEUES0[19:16]
Engine 1 Video N/A N/A MEM_RD_QUEUES0[23:20]
Engine 1 Coeff0 N/A N/A MEM_RD_QUEUES0[27:24]
Engine 1 Coeff1 N/A N/A MEM_RD_QUEUES0[31:28]
Engine 1 Coeff2 N/A N/A MEM_RD_QUEUES1[3:0]
Level Two Title