Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

22.4. Generic Crosspoint IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 327.  Generic Crosspoint IP Registers
Offset Register Access
Parameterization Registers
0x000 VID_PID RO
0x004 VERSION_NUMBER RO
0x008 NUM_INPUTS RO
0x00C NUM_OUTPUTS RO
Core Specific Registers
0x140 REG_OUTPUT_0 RW
0x144 REG_OUTPUT_1 RW
0x148 REG_OUTPUT_2 RW
0x14C REG_OUTPUT_3 RW
0x150 REG_OUTPUT_4 RW
0x154 REG_OUTPUT_5 RW
0x158 REG_OUTPUT_6 RW
0x15C REG_OUTPUT_7 RW
0x160 REG_OUTPUT_8 RW
0x164 REG_OUTPUT_9 RW
0x168 REG_OUTPUT_10 RW
0x16C REG_OUTPUT_11 RW
0x170 REG_OUTPUT_12 RW
0x174 REG_OUTPUT_13 RW
0x178 REG_OUTPUT_14 RW
0x17C REG_OUTPUT_15 RW
0x180 REG_OUTPUT_16 RW
0x184 REG_OUTPUT_17 RW
0x188 REG_OUTPUT_18 RW
0x18C REG_OUTPUT_19 RW
0x190 REG_OUTPUT_20 RW
0x194 REG_OUTPUT_21 RW
0x198 REG_OUTPUT_22 RW
0x19C REG_OUTPUT_23 RW
0x1A0 REG_OUTPUT_24 RW
0x1A4 REG_OUTPUT_25 RW
0x1A8 REG_OUTPUT_26 RW
0x1AC REG_OUTPUT_27 RW
0x1B0 REG_OUTPUT_28 RW
0x1B4 REG_OUTPUT_29 RW
0x1B8 REG_OUTPUT_30 RW
0x1BC REG_OUTPUT_31 RW

Register Bit Descriptions

Table 328.  Vid_pid
Bits Description
31:0 Product Identification Number
Table 329.  Version_number_pid
Bits Description
31:0 IP Version Number
Table 330.  Reg_output_N where N goes from 0 to 31
Bits Description
31:0 Number of the input port to select