2.1. Intel® Quartus® Prime Pro Edition Software
Intel® Quartus® Prime Software
- Starting in V18.1.1, you cannot set the following Advanced I/O Timing assignments as a global setting. You can still use these assignments as pin assignments.
- OUTPUT_IO_TIMING_NEAR_END_VMEAS
- OUTPUT_IO_TIMING_FAR_END_VMEAS
- OUTPUT_IO_TIMING_ENDPOINT
- BOARD_MODEL_NEAR_PULLUP_R
- BOARD_MODEL_NEAR_PULLDOWN_R
- BOARD_MODEL_NEAR_C
- BOARD_MODEL_NEAR_SERIES_R
- BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
- BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
- BOARD_MODEL_NEAR_TLINE_LENGTH
- BOARD_MODEL_TLINE_C_PER_LENGTH
- BOARD_MODEL_TLINE_L_PER_LENGTH
- BOARD_MODEL_TLINE_LENGTH
- BOARD_MODEL_FAR_SERIES_R
- BOARD_MODEL_FAR_C
- BOARD_MODEL_FAR_PULLUP_R
- BOARD_MODEL_FAR_PULLDOWN_R
- BOARD_MODEL_TERMINATION_V
- BOARD_MODEL_NEAR_SERIES_C
- BOARD_MODEL_NEAR_DIFFERENTIAL_R
- BOARD_MODEL_FAR_DIFFERENTIAL_R
Intel® Quartus® Prime Device Support
- Enabled advanced support for Intel® Stratix® 10 1SG211H and 1SG166H device families.
- Enabled full support for Intel® Stratix® 10 1SM16BH, 1SM16CH, 1SM21BH, 1SM21CH, 1ST250E, and 1ST280E device families.
- Enabled SRAM object file (.sof) support for Intel® Stratix® 10 1ST280 and 1ST250 device families.
- The timing model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
- The power model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
Intel® Quartus® Prime Compilation and Design Flows
- The Intel® Quartus® Prime Compiler uses a parallel IP generation scheme now by default. Previously, using parallel IP generation was optional.
- The Enable Early Place flow setting is not supported with "Compile Time" Optimization Mode. The Compilation Dashboard shows status failed for the Fitter (Early Place) module, because it has been skipped in the compilation flow.
Fitter
- Fixed bug with overly restrictive placement check for preserved logic in an incremental compile.
- Improved estimation of Hyper-Registers for device limit resource checking.
- Improved compile time in Quartus placement for Windows.
- Removed “Optimize for High Utilization” option from the “Physical Placement Effort” setting. Changes to improve placement for high utilization designs were incorporated into the default compilation flow.
- Improved compiler to use more accurate estimation for clock resources at the row level thus helping to avoid errors in routing.
- Fixed an issue that could cause the following fitter error to be incorrectly printed in incremental compilations when global signals are driven to partitions and left unused.
Error (18974): Signal is constrained to be routed locally to destination(s), but signal must be routed globally - The Enable Early Place flow setting is not supported with "Compile Time" Optimization Mode. The Compilation Dashboard shows status failed for the Fitter (Early Place) module, because it has been skipped in the compilation flow.
- Fixed incorrect bit settings for 8LUT LUTMASKs in cases where the fitter performs optimizations on them.
Partial Reconfiguration
- Compilation support added to support a hardware issue affecting Intel® Arria® 10 10AX16-10AX32 and 10AS16-10AS32 device families and Intel® Cyclone® 10 devices that use Partial Reconfiguration or EDCRC. The changes ensure that resources that might be susceptible to glitches are not used during these compilations.
- For Intel® Stratix® 10 devices, a POF ID feature is added to help you with PR bitstream incompatibility checks. This feature is turned on by default. To enable this feature for an existing design, you must recompile the design and regenerate your bitstream using Version 18.1.1. PR POF ID must be enabled if you want to enable PR authentication. The maximum number of PR regions is 32 with PR POF ID enabled.
Platform Designer
- Fixed the Parameters tool, which would continuously flicker after changing a parameter, for some video IPs, such as the Color Plane Sequencer II, and Color Space Converter II.
- Platform Designer uses a parallel IP generation scheme now by default. Previously, using parallel IP generation was optional.
Power Analyzer
- For Intel® Stratix® 10 L-tile devices, the power model is updated for VCCIO3V rail. For details, see the Intel® FPGAs and Programmable Devices Knowledge Base.
- The power model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
Programmer
- For Intel® Stratix® 10 devices, fixed the JAM/JBC syntax error for 2 Gb QSPI flash.
- Fixed an internal error that occurred in the Programmer GUI when autodetecting the EPCQA and S25FL flash.
- Fixed an issue where flash smaller than 128 Mb was not detected automatically.
- The complete Design Hash value in .sof file can now be found in the Compilation report, under Assembler -> Device Option -> Design hash.
- Fixed an error in the Intel® Stratix® 10 signing tool, which might cause unexpected behavior when the signing tool hashes the data.
- Fixed an unexpected closing of the Programmer GUI when an error occurred in the signing tool.
- For Intel® Stratix® 10 devices, added support for RSU upgrade and PR compatibility check.
- For Intel® Stratix® 10 devices, added support for signing certificates and allowing key cancel ID of 32-63.
Timing Models
- For Intel® Stratix® 10 devices, the timing model is updated. For details, see the Intel® FPGAs and Programmable Devices Knowledge Base.
- The timing model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.