Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes

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ID 683328
Date 4/17/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes 2. Issues Addressed in Update 1 3. Issues Addressed in Update 2 4. Software Issues Resolved 5. Software Patches Included in Update Releases 6. Known Issues and Workarounds A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes
2. Issues Addressed in Update 1 x
2.1. Intel® Quartus® Prime Pro Edition Software 2.2. Intel® Quartus® Prime Standard Edition Software 2.3. IP and IP Cores 2.4. DSP Builder for Intel® FPGAs 2.5. Intel High Level Synthesis Compiler 2.6. Intel FPGA SDK for OpenCL*
3. Issues Addressed in Update 2 x
3.1. Intel® Quartus® Prime Pro Edition Software 3.2. IP and IP Cores 3.3. Intel FPGA SDK for OpenCL
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes
2. Issues Addressed in Update 1
3. Issues Addressed in Update 2
4. Software Issues Resolved
5. Software Patches Included in Update Releases
6. Known Issues and Workarounds
A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes

2.3. IP and IP Cores

Unless stated otherwise, the following IP issues apply only to the Intel® Quartus® Prime Pro Edition software.

For Intel® Quartus® Prime Standard Edition software, multiple IP cores were fixed to prevent the following error message that occurred when trying open generated IP: 
Failed to launch MegaWizard Plug-In Manager. <IP_name> could not be
found in the specified library paths.

25G Ethernet IP Core

  • For Intel® Quartus® Prime Standard Edition software, updated the alignment marker format of Soft 25G Ethernet to align with the IEEE 802.3by-2016 standard.

40G Ethernet IP Core

  • Fixed an error with the reconfiguration arbitration logic in the hardware example top-level file.

DisplayPort IP Core

  • For Intel® Stratix® 10 devices, enabled Pixel Clock Recovery function.
  • Changed Synopsys Design Constraints to entity-based Synopsys Design Constraints.
  • Cleaned up compilation warnings found in Intel® Stratix® 10 design example with pixel clock recovery.
  • Enabled Intel® Stratix® 10 design example with Pixel Clock Recovery variant.
  • Enabled initiation of Tx in software regardless of the setting of DP_SUPPORT_EDID_PASSTHRU.
  • Fixed an Intel® Arria® 10 design example when no display output occurred in non GPU mode.
  • Enabled extended receiver capabilities when the maximum link rate is HBR3.
  • For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.

External Memory Interface IP Cores

  • For Intel® Cyclone® 10 devices, enabled DDR3x72 support for 10CX085 FBGA672 devices.
  • For Intel® Stratix® 10 devices, added support for DDR4 clamshell layout.

Fixed Point Functions Intel FPGA IP Core

  • The Fixed Point Functions Intel FPGA IP depends on the dspip_recipes library, which was unintentionally removed in Intel® Quartus® Prime Pro Edition Version 18.1. The dspip_recipes library has been restored in Version 18.1.1.

HDMI IP Core

  • For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.

High Bandwidth Memory Interface IP Core

  • Enabled Intel® Stratix® 10 MX production devices.

High Speed Serial Interface (HSSI) IP Core

  • Some configurations of the Intel® Stratix® 10 Transceiver IP with multiple reconfiguration profiles enabled might have more pessimistic timing analysis on data transfers between the transceivers and main fabric. Run the Version 18.1.1 Timing Analyzer on such designs to ensure timing closure.
  • Improved timing driven placement and routing support for reconfigurable HSSI designs.
  • Disabled the use of hyper-pipeline registers in the GUI.

Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Core

  • Fixed signal connections for manual reset mode.
  • Fixed the reset IP option to enable individual channels when individual Tx/Rx is enabled.
  • Disabled the following GUI options:
    • Enable TX fast pipeline registers
    • Enable RX fast pipeline registers
  • Updated the ical and pcal tuning parameters.
  • Improved PHY performance in 3m DAC cables.
  • Enabled BTI protection on the unused slave channels for dual-channel PAM4 Native PHY instances.

Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP Core

  • Removed a redundant character that caused warning message.
  • Fixed an issue where an incorrect clock might be used when AN mode switches to data mode.

Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Core

  • Added multi-segment mode support.
  • Added Number of Segments parameter.
  • Added support for lane and data rate combinations as follows:
    • For Intel® Stratix® 10 L-tile devices:
      • 4 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 8 lanes with 12.5 Gbps lane rates
    • For Intel® Stratix® 10 H-tile devices:
      • 4 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 8 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 10 lanes with 25.3/25.8 Gbps lane rates
    • For Intel® Stratix® 10 E-tile (NRZ) devices:
      • 4 lanes with 6.25/12.5/25.3/25.8 Gbps lane rates
      • 8 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 10 lanes with 25.3/25.8 Gbps lane rates
      • 12 lanes with 10.3125 Gbps lane rate
  • Added the following new transmit user interface signals:
    • itx_eob1
    • itx_eopbits1
    • itx_chan1
  • Added the following new receiver user interface signals:

    • irx_eob1

    • irx_eopbits1

    • irx_chan1

    • irx_err1

    • irx_err

Remote Update IP Core

  • Corrected pinout names to prevent errors during synthesis.

Serial Digital Interface (SDI) II Intel® FPGA IP Core

  • For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.

Triple-Speed Ethernet IP Core

  • For Intel® Quartus® Prime Standard Edition software, fixed an issue preventing generated IP files from being displayed in the IP Catalog.

Virtual JTAG IP Core

  • For Intel® Quartus® Prime Standard Edition software, fixed an issue with possible broken JTAG continuity when a virtual IR access is issued.
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