Visible to Intel only — GUID: mwh1409959579917
Ixiasoft
Visible to Intel only — GUID: mwh1409959579917
Ixiasoft
2.4.1. Inferring RAM functions from HDL Code
Synthesis tools typically consider all signals and variables that have a multi-dimensional array type and then create a RAM block, if applicable. This is based on the way the signals or variables are assigned or referenced in the HDL source description.
Standard synthesis tools recognize single-port and simple dual-port (one read port and one write port) RAM blocks. Some synthesis tools (such as the Intel® Quartus® Prime software) also recognize true dual-port (two read ports and two write ports) RAM blocks that map to the memory blocks in certain Intel FPGA devices.
Some tools (such as the Intel® Quartus® Prime software) also infer memory blocks for array variables and signals that are referenced (read/written) by two indexes, to recognize mixed-width and byte-enabled RAMs for certain coding styles.
Section Content
Use Synchronous Memory Blocks
Avoid Unsupported Reset and Control Conditions
Check Read-During-Write Behavior
Controlling RAM Inference and Implementation
Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior
Single-Clock Synchronous RAM with New Data Read-During-Write Behavior
Simple Dual-Port, Dual-Clock Synchronous RAM
True Dual-Port Synchronous RAM
Mixed-Width Dual-Port RAM
RAM with Byte-Enable Signals
Specifying Initial Memory Contents at Power-Up