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2.1. Using Provided HDL Templates
2.2. Instantiating IP Cores in HDL
2.3. Inferring Multipliers and DSP Functions
2.4. Inferring Memory Functions from HDL Code
2.5. Register and Latch Coding Guidelines
2.6. General Coding Guidelines
2.7. Designing with Low-Level Primitives
2.8. Recommended HDL Coding Styles Revision History
2.4.1.1. Use Synchronous Memory Blocks
2.4.1.2. Avoid Unsupported Reset and Control Conditions
2.4.1.3. Check Read-During-Write Behavior
2.4.1.4. Controlling RAM Inference and Implementation
2.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior
2.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior
2.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM
Verilog HDL Simple Dual-Port, Dual-Clock Synchronous RAM
VHDL Simple Dual-Port, Dual-Clock Synchronous RAM
2.4.1.8. True Dual-Port Synchronous RAM
2.4.1.9. Mixed-Width Dual-Port RAM
2.4.1.10. RAM with Byte-Enable Signals
2.4.1.11. Specifying Initial Memory Contents at Power-Up
2.6.6.1. If Performance is Important, Optimize for Speed
2.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages
2.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge
2.6.6.4. Take Advantage of Latency if Available
2.6.6.5. Save Power by Disabling CRC Blocks When Not in Use
2.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer
3.4.2. Force the Identification of Synchronization Registers
3.4.3. Set the Synchronizer Data Toggle Rate
3.4.4. Optimize Metastability During Fitting
3.4.5. Increase the Length of Synchronizers to Protect and Optimize
3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit
3.4.7. Increase the Number of Stages Used in Synchronizers
3.4.8. Select a Faster Speed Grade Device
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2.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM
With dual-clock designs, synthesis tools cannot accurately infer the read-during-write behavior because it depends on the timing of the two clocks within the target device. Therefore, the read-during-write behavior of the synthesized design is undefined and may differ from your original HDL code.
When Intel® Quartus® Prime integrated synthesis infers this type of RAM, it issues a warning because of the undefined read-during-write behavior.
Verilog HDL Simple Dual-Port, Dual-Clock Synchronous RAM
module simple_dual_port_ram_dual_clock #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) ( input [(DATA_WIDTH-1):0] data, input [(ADDR_WIDTH-1):0] read_addr, write_addr, input we, read_clock, write_clock, output reg [(DATA_WIDTH-1):0] q ); // Declare the RAM variable reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; always @ (posedge write_clock) begin // Write if (we) ram[write_addr] <= data; end always @ (posedge read_clock) begin // Read q <= ram[read_addr]; end endmodule
VHDL Simple Dual-Port, Dual-Clock Synchronous RAM
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dual_clock_ram IS PORT ( clock1, clock2: IN STD_LOGIC; data: IN STD_LOGIC_VECTOR (3 DOWNTO 0); write_address: IN INTEGER RANGE 0 to 31; read_address: IN INTEGER RANGE 0 to 31; we: IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END dual_clock_ram; ARCHITECTURE rtl OF dual_clock_ram IS TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ram_block: MEM; SIGNAL read_address_reg : INTEGER RANGE 0 to 31; BEGIN PROCESS (clock1) BEGIN IF (rising_edge(clock1)) THEN IF (we = '1') THEN ram_block(write_address) <= data; END IF; END IF; END PROCESS; PROCESS (clock2) BEGIN IF (rising_edge(clock2)) THEN q <= ram_block(read_address_reg); read_address_reg <= read_address; END IF; END PROCESS; END rtl;
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