AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

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ID 683317
Date 6/08/2022
Public
Document Table of Contents
Document Table of Contents x
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board x
1.1. Introduction 1.2. Hardware and Software Requirements 1.3. Hardware Design 1.4. Functional Description 1.5. Reference Design 1.6. Document Revision History for AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board 1.7. Appendix
1.4. Functional Description x
1.4.1. DFE Processing in FPGA 1.4.2. JESD204B Subsystem Overview
1.5. Reference Design x
1.5.1. Design Files 1.5.2. Running the Demo with Prebuilt Binaries 1.5.3. Enable Loopback 1.5.4. Configuration Registers
1.5.2. Running the Demo with Prebuilt Binaries x
1.5.2.1. Bringing Up Demo System Using SD Card Image
1.5.2.1. Bringing Up Demo System Using SD Card Image x
1.5.2.1.1. Creating SD Card 1.5.2.1.2. Configuring the Board 1.5.2.1.3. Running the Demo
1.5.4. Configuration Registers x
1.5.4.1. Address Map 1.5.4.2. Status Registers 1.5.4.3. Control Registers 1.5.4.4. PLL Status Registers 1.5.4.5. Base_address_sample_control Registers
1.5.4.1. Address Map x
1.5.4.1.1. Cortex-A9 MPU Address Maps
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

1.5.4.2. Status Registers

Table 4.  Status RegisterAddress: 0xff218040
Bit Register Name Description Attribute Reset Value
31 etile E-tile or not. RO 1’b0
30 Core_pll_cal_busy Cal_busy of fPLL for link_clk and frame_clk. RO 1’b0
...
14:8 N/A Link 2 status signals N/A N/A
[7:1] All_rx_pma_ready

All_tx_pma_ready

Rx_link_error

Tx_link_error

Avst_patchk_data_error

Rx_xcvr_ready

Tx_xcvr_ready

Link 1 status signals RO N/A
0 Core_pll_locked Locked of fPLL for link_clk and frame_clk. RO 1’b1
Level Two Title