1.4.1. DFE Processing in FPGA
The digital front end (DFE) in the FPGA includes the following modules:
- Random access memory (RAM) for TX data generation
- Finite impulse response (FIR) for channel filter
- Half-band filter (HBF) for TX data interpolation
- Gain adjustment for TX data
- Test function
- Single tone
- Increasing sequence
Figure 2. DFE Processing
RAM
In the RAM module, you can store 122880 data under 122.88 Mpbs sample rate, which can deliver about 1 ms 100 MHz NR baseband data in time domain.
You can also write your own TX data into this RAM.
FIR
FIR is used for channel filter with following specifications. This module is implemented using the FIR II Intel® FPGA IP.
- Transmission bandwidth: 98.28 MHz (273 RB * 12 subcarriers * 30 KHz)
- Rejection: 50 dBs
- Ripple: ±0.02 dBs
- Filter order: 384
- Sample rate: 122.88 MHz
- Fmax: 245.76 MHz
Figure 3. FIR Frequency Domain
The following figures show the FIR II Intel® FPGA IP parameter setting in the Intel® Quartus® Prime software. You can modify these parameters based on your specific requirements.
Figure 4. Example FIR II Intel® FPGA IP Parameter Setting: Filter Specification Tab
Figure 5. Example FIR II Intel® FPGA IP Parameter Setting: Coefficient Specification Tab
Figure 6. Example FIR II Intel® FPGA IP Parameter Setting: Input/Output Options Tab
HBF
Use HBF for TX data interpolation with the following specifications, to increase TX data sample rate from 122.88 Mpbs to 245.76 Mbps. This module is implemented using the FIR II Intel® FPGA IP.
- Transmission bandwidth: 98.28 MHz (273 RB * 12 subcarriers * 30 KHz)
- Rejection: More than 80 dBs
- Ripple: ±0.005 dBs
- Filter order: 54
- Sample rate: 245.76 MHz
- Fmax: 245.76 MHz
Figure 7. HBF Frequency Domain
The following figures show the FIR II Intel® FPGA IP parameter setting for HBF. You can modify these parameters based on your specific requirements.
Figure 8. Example FIR II Intel® FPGA IP Parameter Setting for HBF: Filter Specification Tab
Figure 9. Example FIR II Intel® FPGA IP Parameter Setting for HBF: Coefficient Settings Tab
Figure 10. Example FIR II Intel® FPGA IP Parameter Setting for HBF: Input/Output Options Tab
Gain
Use gain for TX data gain adjustment. The gain parameter is a 16 bit data.
Figure 11. Gain
The 0 dB gain parameter is 10’d512. When the gain parameter is larger than 512, the gain is positive. Otherwise, the gain is negative.
Test Function
Test functions in the design include single tone and increasing sequence. You can also add more test data or modify the test functions.
The single tone is based on NCO Intel® FPGA IP, with the default setting is a 5 MHz single tone. The following figure shows the frequency domain and time domain.
Figure 12. NCO Frequency Domain
Figure 13. NCO Time Domain
The following figures show the NCO Intel® FPGA IP parameter setting in the Intel® Quartus® Prime software. You can modify these parameters based on your specific requirement.
Figure 14. Example NCO Intel® FPGA IP Parameter Setting: Architecture Tab
Figure 15. Example NCO Intel® FPGA IP Parameter Setting: Frequency Tab
The increasing sequence is used for JESD204B loop test. You can capture the RX data by using the Signal Tap Logic Analyzer to check if the JESD204B works well.
always @ ( posedge clk )
begin
loop_test_data_i <= loop_test_data_i + 16'd1;
loop_test_data_q <= loop_test_data_q + 16'd2;
end