R-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

ID 683311
Date 7/08/2024
Public

1.12. R-Tile IP for PCI Express IP Core v3.0.0

Table 23.  v3.0.0 2021.10.04
Quartus® Prime Version Description Impact
21.3 Added design example support for the Agilex™ 7 I-Series Development Kit. You can generate the 1x16 design example targeting the Agilex™ 7 I-Series Development Kit for early evaluation. Note that the Debug Toolkit is not available and is planned to be released in a future release of the IP.
Added support to enable ECRC and LCRC error counters. Improved error telemetry capabilities by allowing the counting of ECRC and LCRC errors on a PCIe link.
Table 24.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP -1 -2 -3
16-channel PIPE Direct SCT SCT SCT 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x8/x8 512-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz