R-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

ID 683311
Date 7/08/2024
Public

1.14. R-Tile IP for PCI Express IP Core v1.0.0

Table 27.  v1.0.0 2021.03.29
Quartus® Prime Version Description Impact
21.1 Added support for PCI Express configurations to the R-tile Avalon® Streaming IP. The IP supports Gen5/Gen4/Gen3 x16/x8x8/x4x4x4 Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) configurations.
Added support for PCI Express features to the R-tile Avalon® Streaming IP. The IP supports PCI Express features such as: PRS, LTR, PTM, Completion Timeout, AER, ECRC, AtomicOps.
Added support for PCI Express multi-function and virtualization features to the R-tile Avalon® Streaming IP. The IP supports PCI Express features such as: SR-IOV, ACS, ARI, FLR, TPH, ATS, CII, PASID, VirtIO.
Table 28.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP -1 -2 -3
16-channel PIPE Direct SCT SCT SCT 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x8/x8 512-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Note: Design examples are available only in the x16 EP modes in the 21.1 release of Quartus® Prime.