AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.4. Step 4: Plan Periphery Placement

The Interface Planner helps you to quickly plan device periphery placement. You can directly place elements onto a graphical representation of the device floorplan, while simultaneously validating the placement legality for final implementation. While you place design elements onto the Chip or Package view, the Fitter dynamically guides you to make only legal placements. Interface Planner validates your plan against any existing location assignments that you import from the project. The following sections describe planning for each periphery block.

Follow these steps to setup Interface Planner for periphery placement:

  1. To interactively place IP cores and other design elements in legal locations in the device periphery, click Plan Design on the Flow control. The Plan tab displays a list of your project's design elements, alongside a graphical abstraction of the target device architecture.
    Figure 7.  Intel® Quartus® Prime Pro Edition Interface Planner
  2. On the Plan tab, click Package View and select Package Bottom. These options display a view that shows the pin placement on the left side of the device. This view is similar to the Intel® Quartus® Prime Pro Edition Pin Planner that you use to compare the final results.
    Figure 8. Package Bottom in Package View

Section Content
Plan the External Memory Interface
Plan the PCIe Interface
Plan the SerialLite III Interface
Plan the Transceiver PHY Interface
Complete and Save the Floorplan

Level Two Title