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1.3.4.2. Plan the PCIe* Interface
The Interface Planner helps you to locate available locations and pin placement for the Intel® FPGA IP for PCIe* and the SerialLite III Intel® FPGA IP interfaces. The following sections describe planning for these IP.
Follow these steps to plan the PCIe* interface:
- In Interface Planner, click the IP filter button.
- In the Design Elements list, expand the IP_TOP_I0 block to select the PCIe* dut design element. The design example FPGA_TOP.vhd file specifies to only use the left side of the device.
- Click the >> button next to dut to display Legal Locations for placement. Interface Planner shows one legal location for the left side of the device.
Figure 12. Legal Locations Button
- Double-click the HSSI_DUPLUX_CHANNEL_CLUSTER_24 to place the elements in the floorplan. This placement then assigns this PCIe* IP to this fixed location.
Figure 13. PCIe Fixed Placement