AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.2. Design Example Files

Follow these steps to use the design example files this application note describes:
  1. Download the FPGA_TOP design example project archive file at:

    https://www.intel.com/content/dam/altera-www/global/en_US/others/literature/tt/s10_interface_planner_example.qar

  2. Launch the Intel® Quartus® Prime Pro Edition software.
  3. Click Project > Restore Archived Project.
  4. Select the s10_interface_planner_example.qar Archive name, and then click OK. The following project files restore into the Destination folder (by default, the s10_interface_planner_example_restored directory).
Figure 3. FGPA_TOP Intel® Stratix® 10 Design Example Directories
Table 1.   FPGA_TOP Design Example Files
File Name Description
FPGA_TOP.vhd

Contains the top level of the example design. This is the only file you modify for this application note. You can specify the IP variant you require, and the number of channels if instantiating the IP more than once. You can also control whether channels are on only the left, right, or on both sides of the device.

FPGA_CORE_BLK.vhd

Contains RTL logic that creates reset circuitry inside the FPGA for use when targeting hardware.

FPGA_EMIF_BLK.vhd

Contains one instance of DDR4 External Memory Interface (EMIF) Intel® FPGA IP in x72 bit mode. This is a common configuration. If you require more than one instance of DDR4 memory, copy and instantiate in the FPGA_TOP.vhd file.

FPGA_IO_BLK.vhd

Contains the following common Intel® FPGA IP that connect to general purpose I/O pins:

  • ALTLVDS_RX (DPA, non-DPA, and soft-cdr modes)
  • ALTLVDS_TX
  • PHY Lite
FPGA_IP_BLK.vhd

Contains the following common Intel® FPGA IP:

  • PCIe* (Gen 1/2/3) x1, x4 x8 configurations (scalable by instance)
  • Multi-Rate Ethernet (scalable using single channel)
  • 10G Base-KR (scalable using single channel)
  • SerialLite III (scalable using single channel)
  • LL 40G (scalable by instance)
  • Interlaken* 100G (scalable by instance)
  • JESD204B (scalable using single channel)
Level Two Title