Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/13/2021
Public

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Document Table of Contents

VERILOG_MACRO

Defines Verilog HDL macro - same as `define directive

Type

String

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

Syntax


set_global_assignment -name VERILOG_MACRO <value>